179 lines
7.1 KiB
VHDL
179 lines
7.1 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
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--
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-------------------------------------------------------------------------------
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--
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-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
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--
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-- Note that this file is copyrighted, and is not supposed to be used in other
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-- projects without written permission from the author.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity wave_map is
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generic (
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g_num_voices : integer := 8; -- 8 or 16, clock should then be 8 or 16 MHz, too!
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g_sample_bits : integer := 8 );
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port (
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clock : in std_logic;
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reset : in std_logic;
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osc_val : in unsigned(23 downto 0);
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carry_20 : in std_logic;
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msb_other: in std_logic := '0';
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ring_mod : in std_logic := '0';
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test : in std_logic := '0';
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voice_i : in unsigned(3 downto 0);
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comb_mode: in std_logic;
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enable_i : in std_logic;
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wave_sel : in std_logic_vector(3 downto 0);
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sq_width : in unsigned(11 downto 0);
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voice_o : out unsigned(3 downto 0);
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enable_o : out std_logic;
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wave_out : out unsigned(g_sample_bits-1 downto 0) );
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end wave_map;
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architecture Gideon of wave_map is
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type noise_array_t is array (natural range <>) of unsigned(22 downto 0);
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signal noise_reg : noise_array_t(0 to g_num_voices-1) := (others => (0 => '1', others => '0'));
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type voice_array_t is array (natural range <>) of unsigned(g_sample_bits-1 downto 0);
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signal voice_reg : voice_array_t(0 to g_num_voices-1) := (others => (others => '0'));
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type t_byte_array is array(natural range <>) of unsigned(7 downto 0);
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constant c_wave_TP : t_byte_array(0 to 255) := (
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16#FF# => X"FF", 16#F7# => X"F7", 16#EF# => X"EF", 16#E7# => X"E0",
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16#FE# => X"FE", 16#F6# => X"F0", 16#EE# => X"E0", 16#E6# => X"00",
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16#FD# => X"FD", 16#F5# => X"FD", 16#ED# => X"E0", 16#E5# => X"00",
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16#FC# => X"F8", 16#F4# => X"80", 16#EC# => X"00", 16#E4# => X"00",
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16#FB# => X"FB", 16#F3# => X"F0", 16#EB# => X"E0", 16#E3# => X"00",
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16#FA# => X"F8", 16#F2# => X"08", 16#EA# => X"00", 16#E2# => X"00",
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16#F9# => X"F0", 16#F1# => X"00", 16#E9# => X"00", 16#E1# => X"00",
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16#F8# => X"80", 16#F0# => X"00", 16#E8# => X"00", 16#E0# => X"00",
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16#DF# => X"DF", 16#DE# => X"D0", 16#DD# => X"C0", 16#DB# => X"C0",
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16#D7# => X"C0", 16#CF# => X"C0", 16#BF# => X"BF", 16#BE# => X"B0",
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16#BD# => X"A0", 16#B9# => X"80", 16#B7# => X"80", 16#AF# => X"80",
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16#7F# => X"7F", 16#7E# => X"70", 16#7D# => X"70", 16#7B# => X"60",
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16#77# => X"40", others => X"00" );
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constant c_wave_TS : t_byte_array(0 to 255) := (
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16#7F# => X"1E", 16#FE# => X"18", 16#FF# => X"3E", others => X"00" );
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begin
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process(clock)
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variable noise_tmp : unsigned(22 downto 0);
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variable voice_tmp : unsigned(g_sample_bits-1 downto 0);
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variable triangle : unsigned(g_sample_bits-1 downto 0);
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variable square : unsigned(g_sample_bits-1 downto 0);
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variable sawtooth : unsigned(g_sample_bits-1 downto 0);
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variable out_tmp : unsigned(g_sample_bits-1 downto 0);
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variable new_bit : std_logic;
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begin
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if rising_edge(clock) then
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-- take top of list
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voice_tmp := voice_reg(0);
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noise_tmp := noise_reg(0);
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if reset='1' or test='1' then
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noise_tmp := (others => '1'); -- seed not equal to zero
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elsif carry_20='1' then
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new_bit := noise_tmp(22) xor noise_tmp(21) xor noise_tmp(20) xor noise_tmp(15);
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noise_tmp := noise_tmp(21 downto 0) & new_bit;
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end if;
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if osc_val(23)='1' then
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triangle := not osc_val(22 downto 23-g_sample_bits);
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else
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triangle := osc_val(22 downto 23-g_sample_bits);
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end if;
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if ring_mod='1' and msb_other='0' then
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triangle := not triangle;
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end if;
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sawtooth := osc_val(23 downto 24-g_sample_bits);
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if osc_val(23 downto 12) < sq_width then
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square := (others => '0');
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else
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square := (others => '1');
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end if;
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out_tmp := (others => '0');
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case wave_sel is
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when X"0" =>
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out_tmp := voice_tmp;
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when X"1" =>
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out_tmp := triangle;
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when X"2" =>
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out_tmp := sawtooth;
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when X"3" =>
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if comb_mode='0' then
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out_tmp(g_sample_bits-1 downto g_sample_bits-8) :=
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c_wave_TS(to_integer(osc_val(23 downto 23-g_sample_bits)));
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else -- 8580
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out_tmp := triangle and sawtooth;
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end if;
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when X"4" =>
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out_tmp := square;
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when X"5" => -- combined triangle and square
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if comb_mode='0' then
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if square(0)='1' then
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out_tmp(g_sample_bits-1 downto g_sample_bits-8) :=
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c_wave_TP(to_integer(triangle(g_sample_bits-1 downto g_sample_bits-8)));
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end if;
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else -- 8580
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out_tmp := triangle and square;
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end if;
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when X"6" => -- combined saw and pulse
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if comb_mode='1' then
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out_tmp := sawtooth and square;
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end if;
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when X"7" => -- combined triangle, saw and pulse
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if comb_mode='1' then
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out_tmp := triangle and sawtooth and square;
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end if;
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when X"8" =>
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out_tmp(g_sample_bits-1) := noise_tmp(22); -- unsure.. 21?
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out_tmp(g_sample_bits-2) := noise_tmp(20);
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out_tmp(g_sample_bits-3) := noise_tmp(16);
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out_tmp(g_sample_bits-4) := noise_tmp(13);
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out_tmp(g_sample_bits-5) := noise_tmp(11);
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out_tmp(g_sample_bits-6) := noise_tmp(7);
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out_tmp(g_sample_bits-7) := noise_tmp(4);
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out_tmp(g_sample_bits-8) := noise_tmp(2);
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-- when X"9"|X"A"|X"B"|X"C"|X"D"|X"E"|X"F" =>
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-- out_tmp := noise_tmp(20 downto 21-g_sample_bits);
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-- noise_tmp := (others => '0');
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when others =>
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null;
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end case;
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if enable_i='1' then
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noise_reg(g_num_voices-1) <= noise_tmp;
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noise_reg(0 to g_num_voices-2) <= noise_reg(1 to g_num_voices-1);
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voice_reg(g_num_voices-1) <= out_tmp;
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voice_reg(0 to g_num_voices-2) <= voice_reg(1 to g_num_voices-1);
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end if;
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--out_tmp(out_tmp'high) := not out_tmp(out_tmp'high);
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wave_out <= unsigned(out_tmp);
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voice_o <= voice_i;
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enable_o <= enable_i;
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end if;
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end process;
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end Gideon;
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