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https://github.com/tebl/RC6502-Apple-1-Replica.git
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Fixed footprint error
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parent
77ffaff523
commit
294df9eda7
@ -1 +1,109 @@
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(kicad_pcb (version 4) (host kicad "dummy file") )
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(kicad_pcb (version 4) (host pcbnew 4.0.7)
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(general
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(links 0)
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(no_connects 0)
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(area 52.629999 44.374999 152.475001 144.220001)
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(thickness 1.6)
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(drawings 4)
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(tracks 0)
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(zones 0)
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(modules 0)
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(nets 1)
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)
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(page A4)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(32 B.Adhes user)
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(33 F.Adhes user)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(41 Cmts.User user)
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(42 Eco1.User user)
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(43 Eco2.User user)
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(44 Edge.Cuts user)
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(45 Margin user)
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(46 B.CrtYd user)
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(47 F.CrtYd user)
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(48 B.Fab user)
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(49 F.Fab user)
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)
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(setup
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(last_trace_width 0.25)
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(trace_clearance 0.2)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.2)
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(segment_width 0.2)
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(edge_width 0.15)
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(via_size 0.6)
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(via_drill 0.4)
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(via_min_size 0.4)
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(via_min_drill 0.3)
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(uvia_size 0.3)
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(uvia_drill 0.1)
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(uvias_allowed no)
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(uvia_min_size 0.2)
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(uvia_min_drill 0.1)
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(pcb_text_width 0.3)
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(pcb_text_size 1.5 1.5)
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(mod_edge_width 0.15)
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(mod_text_size 1 1)
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(mod_text_width 0.15)
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(pad_size 1.524 1.524)
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(pad_drill 0.762)
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(pad_to_mask_clearance 0.2)
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(aux_axis_origin 0 0)
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(visible_elements 7FFFFFFF)
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(pcbplotparams
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(layerselection 0x00030_80000001)
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(usegerberextensions false)
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(excludeedgelayer true)
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(linewidth 0.100000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15)
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(hpglpenoverlay 2)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory ""))
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)
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(net 0 "")
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(net_class Default "This is the default net class."
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(clearance 0.2)
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(trace_width 0.25)
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(via_dia 0.6)
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(via_drill 0.4)
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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)
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(gr_line (start 151.765 144.145) (end 52.705 144.145) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 151.765 44.45) (end 52.705 44.45) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 151.765 144.145) (end 151.765 44.45) (angle 90) (layer Edge.Cuts) (width 0.15))
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(gr_line (start 52.705 44.45) (end 52.705 144.145) (angle 90) (layer Edge.Cuts) (width 0.15))
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)
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1111
RC6502 VDU/RC6502 VDU.net
Normal file
1111
RC6502 VDU/RC6502 VDU.net
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
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update=04/12/2018 20:31:54
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update=04/12/2018 21:30:28
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version=1
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last_client=kicad
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[pcbnew]
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@ -23,8 +23,6 @@ ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[general]
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version=1
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[eeschema]
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version=1
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LibDir=
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@ -66,3 +64,5 @@ LibName34=D:/ownCloud/Documents/Projects/RC6502/Templates/mounting
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LibName35=D:/ownCloud/Documents/Projects/RC6502/Templates/oscillator
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LibName36=D:/ownCloud/Documents/Projects/RC6502/Templates/mc6847
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LibName37=D:/ownCloud/Documents/Projects/RC6502/Templates/rca_plug
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[general]
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version=1
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@ -334,7 +334,7 @@ U 1 1 5C045951
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P 10250 1975
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F 0 "J4" V 10350 1975 50 0000 C CNN
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F 1 "Hole" V 10350 1975 50 0001 C CNN
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F 2 "rc6502:Mounting" H 10250 1975 50 0001 C CNN
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F 2 "mounting:Mounting" H 10250 1975 50 0001 C CNN
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F 3 "" H 10250 1975 50 0001 C CNN
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1 10250 1975
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0 1 1 0
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@ -345,7 +345,7 @@ U 1 1 5C045952
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P 10500 1975
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F 0 "J6" V 10600 1975 50 0000 C CNN
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F 1 "Hole" V 10600 1975 50 0001 C CNN
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F 2 "rc6502:Mounting" H 10500 1975 50 0001 C CNN
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F 2 "mounting:Mounting" H 10500 1975 50 0001 C CNN
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F 3 "" H 10500 1975 50 0001 C CNN
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1 10500 1975
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0 1 1 0
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@ -356,7 +356,7 @@ U 1 1 5C045953
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P 10375 1975
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F 0 "J5" V 10475 1975 50 0000 C CNN
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F 1 "Hole" V 10475 1975 50 0001 C CNN
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F 2 "rc6502:Mounting" H 10375 1975 50 0001 C CNN
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F 2 "mounting:Mounting" H 10375 1975 50 0001 C CNN
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F 3 "" H 10375 1975 50 0001 C CNN
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1 10375 1975
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0 1 1 0
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@ -367,7 +367,7 @@ U 1 1 5C045954
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P 10625 1975
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F 0 "J7" V 10725 1975 50 0000 C CNN
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F 1 "Hole" V 10725 1975 50 0001 C CNN
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F 2 "rc6502:Mounting" H 10625 1975 50 0001 C CNN
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F 2 "mounting:Mounting" H 10625 1975 50 0001 C CNN
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F 3 "" H 10625 1975 50 0001 C CNN
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1 10625 1975
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0 1 1 0
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@ -1,3 +1,4 @@
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(fp_lib_table
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(lib (name rca)(type KiCad)(uri D:/ownCloud/Documents/Projects/RC6502/Templates/rca.pretty)(options "")(descr ""))
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(lib (name mounting)(type KiCad)(uri D:/ownCloud/Documents/Projects/RC6502/Templates/mounting.pretty)(options "")(descr ""))
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)
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14
Templates/mounting.pretty/1pin.kicad_mod
Normal file
14
Templates/mounting.pretty/1pin.kicad_mod
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@ -0,0 +1,14 @@
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(module Connectors:1pin (layer F.Cu) (tedit 59414318)
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(descr "module 1 pin (ou trou mecanique de percage)")
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(tags DEV)
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(fp_text reference REF** (at 0 -3.048) (layer F.SilkS)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value 1pin (at 0 3) (layer F.Fab)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_circle (center 0 0) (end 2 0.8) (layer F.Fab) (width 0.1))
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(fp_circle (center 0 0) (end 2.6 0) (layer F.CrtYd) (width 0.05))
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(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.12))
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(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.048) (layers *.Cu *.Mask))
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)
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14
Templates/mounting.pretty/Mounting.kicad_mod
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14
Templates/mounting.pretty/Mounting.kicad_mod
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@ -0,0 +1,14 @@
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(module Mounting (layer F.Cu) (tedit 594143BA)
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(descr "module 1 pin (ou trou mecanique de percage)")
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(tags DEV)
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(fp_text reference Hole** (at 0 -3.81) (layer F.SilkS) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value 1pin (at 0 3.81) (layer F.Fab) hide
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_circle (center 0 0) (end 2 0.8) (layer F.Fab) (width 0.1))
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(fp_circle (center 0 0) (end 2.6 0) (layer F.CrtYd) (width 0.05))
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(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.12))
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(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask))
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)
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