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Fixed RAM board block select logic

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This commit is contained in:
Unknown 2019-02-16 22:24:28 +01:00
parent 070d9f271e
commit bcedf3cb12
18 changed files with 2443 additions and 2073 deletions
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76
RC6502 RAM/RC6502 RAM-cache.lib
View File

@ -50,52 +50,48 @@ X ~ 13 -600 -100 370 R 50 50 4 2 I I
ENDDRAW
ENDDEF
#
# 74LS02
# 74LS08
#
DEF 74LS02 U 0 30 Y Y 4 F N
DEF 74LS08 U 0 30 Y Y 4 F N
F0 "U" 0 50 50 H V C CNN
F1 "74LS02" 50 -50 50 H V C CNN
F1 "74LS08" 0 -50 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74HC02 74HCT02 7402 74LS28
$FPLIST
SO14*
14DIP*
$ENDFPLIST
ALIAS 74LS09
DRAW
X GND 7 -200 -200 0 U 40 40 0 0 W N
X VCC 14 -200 200 0 D 40 40 0 0 W N
A -470 0 262 496 -496 0 1 8 N -300 200 -300 -200
A -1 -127 327 898 228 0 1 8 N 0 200 300 0
A -1 128 327 -230 -898 0 1 8 N 300 0 0 -200
P 2 0 1 8 -300 -200 0 -200 N
P 2 0 1 8 -300 200 0 200 N
X ~ 1 600 0 300 L 50 50 1 1 O I
X ~ 2 -600 100 370 R 50 50 1 1 I
X ~ 3 -600 -100 370 R 50 50 1 1 I
X ~ 4 600 0 300 L 50 50 2 1 O I
X ~ 5 -600 100 370 R 50 50 2 1 I
X ~ 6 -600 -100 370 R 50 50 2 1 I
X ~ 8 -600 100 370 R 50 50 3 1 I
X ~ 9 -600 -100 370 R 50 50 3 1 I
X ~ 10 600 0 300 L 50 50 3 1 O I
X ~ 11 -600 100 370 R 50 50 4 1 I
X ~ 12 -600 -100 370 R 50 50 4 1 I
X ~ 13 600 0 300 L 50 50 4 1 O I
A 100 0 200 896 -896 0 2 8 N 101 200 101 -199
P 4 0 2 8 100 200 -300 200 -300 -200 100 -200 N
X ~ 1 600 0 300 L 50 50 1 2 O
X ~ 2 -600 100 300 R 50 50 1 2 I I
X ~ 3 -600 -100 300 R 50 50 1 2 I I
X ~ 4 600 0 300 L 50 50 2 2 O
X ~ 5 -600 100 300 R 50 50 2 2 I I
X ~ 6 -600 -100 300 R 50 50 2 2 I I
X ~ 8 -600 100 300 R 50 50 3 2 I I
X ~ 9 -600 -100 300 R 50 50 3 2 I I
X ~ 10 600 0 300 L 50 50 3 2 O
X ~ 11 -600 100 300 R 50 50 4 2 I I
X ~ 12 -600 -100 300 R 50 50 4 2 I I
X ~ 13 600 0 300 L 50 50 4 2 O
X VCC 14 -200 200 0 U 40 40 0 0 W N
A 100 0 200 896 -896 0 1 0 N 101 200 101 -199
P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N
X ~ 1 -600 100 300 R 50 50 1 1 I
X ~ 2 -600 -100 300 R 50 50 1 1 I
X ~ 3 600 0 300 L 50 50 1 1 O
X ~ 4 -600 100 300 R 50 50 2 1 I
X ~ 5 -600 -100 300 R 50 50 2 1 I
X ~ 6 600 0 300 L 50 50 2 1 O
X ~ 8 600 0 300 L 50 50 3 1 O
X ~ 9 -600 100 300 R 50 50 3 1 I
X ~ 10 -600 -100 300 R 50 50 3 1 I
X ~ 11 600 0 300 L 50 50 4 1 O
X ~ 12 -600 100 300 R 50 50 4 1 I
X ~ 13 -600 -100 300 R 50 50 4 1 I
A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198
A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2
A 4 -120 320 906 221 0 2 0 N 2 200 300 0
P 2 0 2 0 -300 -200 0 -200 N
P 2 0 2 0 -300 200 0 200 N
X ~ 1 -600 100 370 R 50 50 1 2 I I
X ~ 2 -600 -100 370 R 50 50 1 2 I I
X ~ 3 600 0 300 L 50 50 1 2 O I
X ~ 4 -600 100 370 R 50 50 2 2 I I
X ~ 5 -600 -100 370 R 50 50 2 2 I I
X ~ 6 600 0 300 L 50 50 2 2 O I
X ~ 8 600 0 300 L 50 50 3 2 O I
X ~ 9 -600 100 370 R 50 50 3 2 I I
X ~ 10 -600 -100 370 R 50 50 3 2 I I
X ~ 11 600 0 300 L 50 50 4 2 O I
X ~ 12 -600 100 370 R 50 50 4 2 I I
X ~ 13 -600 -100 370 R 50 50 4 2 I I
ENDDRAW
ENDDEF
#

1508
RC6502 RAM/RC6502 RAM.kicad_pcb
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File diff suppressed because it is too large Load Diff

292
RC6502 RAM/RC6502 RAM.net
View File

@ -1,7 +1,7 @@
(export (version D)
(design
(source "D:/ownCloud/Documents/Projects/RC6502/RC6502 RAM/RC6502 RAM.sch")
(date "22/12/2018 18:14:11")
(source "D:/owncloud/Documents/Projects/RC6502/RC6502 RAM/RC6502 RAM.sch")
(date "16/02/2019 19:37:20")
(tool "Eeschema 4.0.7")
(sheet (number 1) (name /) (tstamps /)
(title_block
@ -75,12 +75,6 @@
(libsource (lib device) (part Jumper_NC_Dual))
(sheetpath (names /) (tstamps /))
(tstamp 5C1D94D7))
(comp (ref U3)
(value 74LS02)
(footprint Housings_DIP:DIP-14_W7.62mm_Socket)
(libsource (lib 74xx) (part 74LS02))
(sheetpath (names /) (tstamps /))
(tstamp 5C1DAB94))
(comp (ref JP4)
(value CS1_EN)
(footprint Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm)
@ -123,12 +117,6 @@
(libsource (lib device) (part Jumper_NC_Dual))
(sheetpath (names /) (tstamps /))
(tstamp 5C1DC596))
(comp (ref U4)
(value 74LS02)
(footprint Housings_DIP:DIP-14_W7.62mm_Socket)
(libsource (lib 74xx) (part 74LS02))
(sheetpath (names /) (tstamps /))
(tstamp 5C1DE352))
(comp (ref C1)
(value 100nF)
(footprint Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm)
@ -152,7 +140,19 @@
(footprint Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm)
(libsource (lib device) (part Jumper_NC_Dual))
(sheetpath (names /) (tstamps /))
(tstamp 5C1ECAEA)))
(tstamp 5C1ECAEA))
(comp (ref U3)
(value 74LS08)
(footprint Housings_DIP:DIP-14_W7.62mm_Socket)
(libsource (lib 74xx) (part 74LS08))
(sheetpath (names /) (tstamps /))
(tstamp 5C68602F))
(comp (ref U4)
(value 74LS08)
(footprint Housings_DIP:DIP-14_W7.62mm_Socket)
(libsource (lib 74xx) (part 74LS08))
(sheetpath (names /) (tstamps /))
(tstamp 5C687BF2)))
(libparts
(libpart (lib 74xx) (part 74LS00)
(aliases
@ -182,33 +182,27 @@
(pin (num 12) (name ~) (type input))
(pin (num 13) (name ~) (type input))
(pin (num 14) (name VCC) (type power_in))))
(libpart (lib 74xx) (part 74LS02)
(libpart (lib 74xx) (part 74LS08)
(aliases
(alias 74HC02)
(alias 74HCT02)
(alias 7402)
(alias 74LS28))
(description "Quad Nor2")
(footprints
(fp SO14*)
(fp 14DIP*))
(alias 74LS09))
(description "Quad And2")
(fields
(field (name Reference) U)
(field (name Value) 74LS02))
(field (name Value) 74LS08))
(pins
(pin (num 1) (name ~) (type output))
(pin (num 1) (name ~) (type input))
(pin (num 2) (name ~) (type input))
(pin (num 3) (name ~) (type input))
(pin (num 4) (name ~) (type output))
(pin (num 3) (name ~) (type output))
(pin (num 4) (name ~) (type input))
(pin (num 5) (name ~) (type input))
(pin (num 6) (name ~) (type input))
(pin (num 6) (name ~) (type output))
(pin (num 7) (name GND) (type power_in))
(pin (num 8) (name ~) (type input))
(pin (num 8) (name ~) (type output))
(pin (num 9) (name ~) (type input))
(pin (num 10) (name ~) (type output))
(pin (num 11) (name ~) (type input))
(pin (num 10) (name ~) (type input))
(pin (num 11) (name ~) (type output))
(pin (num 12) (name ~) (type input))
(pin (num 13) (name ~) (type output))
(pin (num 13) (name ~) (type input))
(pin (num 14) (name VCC) (type power_in))))
(libpart (lib 74xx) (part 74LS138)
(description "Decoder 3 to 8 (active low outputs)")
@ -348,143 +342,143 @@
(pin (num 38) (name P38) (type NotConnected))
(pin (num 39) (name P39) (type NotConnected)))))
(libraries
(library (logical memory)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\memory.lib"))
(library (logical device)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\device.lib"))
(library (logical 74xx)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\74xx.lib"))
(library (logical memory)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\memory.lib"))
(library (logical rc6502_backplane)
(uri D:\ownCloud\Documents\Projects\RC6502\Templates\rc6502_backplane.lib))
(library (logical device)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\device.lib")))
(uri D:\ownCloud\Documents\Projects\RC6502\Templates\rc6502_backplane.lib)))
(nets
(net (code 1) (name "Net-(JP6-Pad2)")
(node (ref JP6) (pin 2))
(node (ref U3) (pin 6)))
(net (code 2) (name "Net-(JP5-Pad2)")
(node (ref JP5) (pin 2))
(node (ref U3) (pin 5)))
(net (code 1) (name "Net-(JP8-Pad2)")
(node (ref JP8) (pin 2))
(node (ref U3) (pin 10)))
(net (code 2) (name "Net-(JP7-Pad2)")
(node (ref U3) (pin 9))
(node (ref JP7) (pin 2)))
(net (code 3) (name VCC)
(node (ref C4) (pin 1))
(node (ref JP3) (pin 1))
(node (ref C1) (pin 1))
(node (ref C4) (pin 1))
(node (ref C5) (pin 1))
(node (ref JP13) (pin 1))
(node (ref U3) (pin 14))
(node (ref JP4) (pin 1))
(node (ref U4) (pin 14))
(node (ref C3) (pin 1))
(node (ref U1) (pin 28))
(node (ref J3) (pin 18))
(node (ref JP11) (pin 3))
(node (ref U2) (pin 16))
(node (ref U5) (pin 14))
(node (ref JP7) (pin 1))
(node (ref C2) (pin 1))
(node (ref JP3) (pin 1))
(node (ref JP6) (pin 1))
(node (ref JP8) (pin 1))
(node (ref JP4) (pin 1))
(node (ref U3) (pin 14))
(node (ref JP5) (pin 1))
(node (ref JP12) (pin 1)))
(net (code 4) (name ~CS3)
(node (ref JP6) (pin 1))
(node (ref JP11) (pin 3))
(node (ref U5) (pin 14))
(node (ref JP8) (pin 1))
(node (ref JP12) (pin 1))
(node (ref U2) (pin 16))
(node (ref C3) (pin 1))
(node (ref J3) (pin 18))
(node (ref U1) (pin 28))
(node (ref JP13) (pin 1)))
(net (code 4) (name ~CS4)
(node (ref JP7) (pin 3))
(node (ref U2) (pin 11)))
(net (code 5) (name ~CS5)
(node (ref U2) (pin 10))
(node (ref JP8) (pin 3)))
(net (code 6) (name "Net-(JP5-Pad2)")
(node (ref U3) (pin 4))
(node (ref JP5) (pin 2)))
(net (code 7) (name "Net-(JP6-Pad2)")
(node (ref U3) (pin 5))
(node (ref JP6) (pin 2)))
(net (code 8) (name ~CS3)
(node (ref U2) (pin 12))
(node (ref JP6) (pin 3)))
(net (code 5) (name GND)
(node (ref C2) (pin 2))
(node (ref U2) (pin 5))
(node (ref C5) (pin 2))
(node (ref C3) (pin 2))
(node (ref U2) (pin 4))
(node (ref U1) (pin 14))
(node (ref U4) (pin 7))
(node (ref U2) (pin 8))
(node (ref U4) (pin 11))
(node (ref U3) (pin 7))
(node (ref U4) (pin 12))
(node (ref U5) (pin 7))
(node (ref J3) (pin 17))
(node (ref C1) (pin 2))
(node (ref C4) (pin 2)))
(net (code 6) (name ~CS2)
(node (ref U2) (pin 13))
(node (ref JP5) (pin 3)))
(net (code 7) (name "Net-(JP8-Pad2)")
(node (ref JP8) (pin 2))
(node (ref U3) (pin 9)))
(net (code 8) (name ~CS5)
(node (ref JP8) (pin 3))
(node (ref U2) (pin 10)))
(net (code 9) (name "Net-(JP7-Pad2)")
(node (ref U3) (pin 8))
(node (ref JP7) (pin 2)))
(net (code 10) (name ~CS4)
(node (ref U2) (pin 11))
(node (ref JP7) (pin 3)))
(net (code 11) (name ~CS1)
(node (ref JP4) (pin 3))
(node (ref U2) (pin 14)))
(net (code 12) (name ~CS0)
(node (ref JP3) (pin 3))
(node (ref U2) (pin 15)))
(net (code 13) (name ~CS7)
(net (code 9) (name "Net-(JP12-Pad2)")
(node (ref JP12) (pin 2))
(node (ref U3) (pin 12)))
(net (code 10) (name "Net-(JP13-Pad2)")
(node (ref U3) (pin 13))
(node (ref JP13) (pin 2)))
(net (code 11) (name ~CS7)
(node (ref U2) (pin 7))
(node (ref JP13) (pin 3)))
(net (code 14) (name ~CS6)
(node (ref JP12) (pin 3))
(node (ref U2) (pin 9)))
(net (code 15) (name "Net-(JP2-Pad1)")
(node (ref JP2) (pin 1))
(node (ref U1) (pin 1)))
(net (code 16) (name "Net-(JP1-Pad1)")
(net (code 12) (name ~CS6)
(node (ref U2) (pin 9))
(node (ref JP12) (pin 3)))
(net (code 13) (name ~CS2)
(node (ref JP5) (pin 3))
(node (ref U2) (pin 13)))
(net (code 14) (name ~CS1)
(node (ref JP4) (pin 3))
(node (ref U2) (pin 14)))
(net (code 15) (name ~CS0)
(node (ref JP3) (pin 3))
(node (ref U2) (pin 15)))
(net (code 16) (name "Net-(JP2-Pad1)")
(node (ref U1) (pin 1))
(node (ref JP2) (pin 1)))
(net (code 17) (name "Net-(JP1-Pad1)")
(node (ref U1) (pin 26))
(node (ref JP1) (pin 1)))
(net (code 17) (name A14)
(net (code 18) (name A14)
(node (ref JP2) (pin 2))
(node (ref J3) (pin 2))
(node (ref U2) (pin 3)))
(net (code 18) (name A13)
(node (ref JP1) (pin 2))
(node (ref U2) (pin 3))
(node (ref J3) (pin 2)))
(net (code 19) (name A13)
(node (ref J3) (pin 3))
(node (ref JP1) (pin 2))
(node (ref U2) (pin 2)))
(net (code 19) (name "Net-(JP3-Pad2)")
(node (ref JP3) (pin 2))
(node (ref U3) (pin 2)))
(net (code 20) (name "Net-(JP4-Pad2)")
(node (ref JP4) (pin 2))
(node (ref U3) (pin 3)))
(net (code 21) (name ~CS)
(node (ref U1) (pin 20))
(node (ref U3) (pin 2)))
(net (code 21) (name "Net-(JP3-Pad2)")
(node (ref JP3) (pin 2))
(node (ref U3) (pin 1)))
(net (code 22) (name GND)
(node (ref U1) (pin 14))
(node (ref U5) (pin 7))
(node (ref J3) (pin 17))
(node (ref C2) (pin 2))
(node (ref C3) (pin 2))
(node (ref U2) (pin 4))
(node (ref U2) (pin 5))
(node (ref U2) (pin 8))
(node (ref C5) (pin 2))
(node (ref C1) (pin 2))
(node (ref C4) (pin 2))
(node (ref U4) (pin 7))
(node (ref U4) (pin 12))
(node (ref U4) (pin 13))
(node (ref U3) (pin 7)))
(net (code 23) (name "Net-(U4-Pad11)")
(node (ref U4) (pin 11)))
(net (code 24) (name "Net-(U4-Pad10)")
(node (ref U4) (pin 6))
(node (ref U4) (pin 10)))
(net (code 22) (name "Net-(U4-Pad1)")
(node (ref U4) (pin 8))
(net (code 25) (name "Net-(U4-Pad3)")
(node (ref U4) (pin 3))
(node (ref U4) (pin 9)))
(net (code 26) (name "Net-(U3-Pad11)")
(node (ref U3) (pin 11))
(node (ref U4) (pin 5)))
(net (code 27) (name "Net-(U3-Pad8)")
(node (ref U4) (pin 4))
(node (ref U3) (pin 8)))
(net (code 28) (name "Net-(U3-Pad6)")
(node (ref U3) (pin 6))
(node (ref U4) (pin 2)))
(net (code 29) (name "Net-(U3-Pad3)")
(node (ref U3) (pin 3))
(node (ref U4) (pin 1)))
(net (code 23) (name "Net-(JP9-Pad3)")
(net (code 30) (name ~CS)
(node (ref U1) (pin 20))
(node (ref U4) (pin 8)))
(net (code 31) (name "Net-(JP9-Pad3)")
(node (ref U5) (pin 3))
(node (ref JP9) (pin 3)))
(net (code 24) (name E3)
(net (code 32) (name E3)
(node (ref JP9) (pin 2))
(node (ref U2) (pin 6)))
(net (code 25) (name "Net-(U4-Pad13)")
(node (ref U4) (pin 13)))
(net (code 26) (name "Net-(JP12-Pad2)")
(node (ref JP12) (pin 2))
(node (ref U3) (pin 11)))
(net (code 27) (name "Net-(JP13-Pad2)")
(node (ref JP13) (pin 2))
(node (ref U3) (pin 12)))
(net (code 28) (name "Net-(U4-Pad4)")
(node (ref U4) (pin 9))
(node (ref U4) (pin 4)))
(net (code 29) (name "Net-(U3-Pad13)")
(node (ref U4) (pin 6))
(node (ref U3) (pin 13)))
(net (code 30) (name "Net-(U3-Pad10)")
(node (ref U3) (pin 10))
(node (ref U4) (pin 5)))
(net (code 31) (name "Net-(U3-Pad1)")
(node (ref U3) (pin 1))
(node (ref U4) (pin 2)))
(net (code 32) (name "Net-(U3-Pad4)")
(node (ref U4) (pin 3))
(node (ref U3) (pin 4)))
(net (code 33) (name "Net-(J3-Pad25)")
(node (ref J3) (pin 25)))
(net (code 34) (name "Net-(J3-Pad23)")
@ -504,13 +498,13 @@
(net (code 41) (name "Net-(J3-Pad37)")
(node (ref J3) (pin 37)))
(net (code 42) (name A15)
(node (ref U5) (pin 1))
(node (ref U5) (pin 2))
(node (ref U5) (pin 1))
(node (ref J3) (pin 1))
(node (ref JP9) (pin 1)))
(net (code 43) (name D6)
(node (ref J3) (pin 33))
(node (ref U1) (pin 18)))
(node (ref U1) (pin 18))
(node (ref J3) (pin 33)))
(net (code 44) (name D5)
(node (ref U1) (pin 17))
(node (ref J3) (pin 32)))
@ -518,11 +512,11 @@
(node (ref U1) (pin 16))
(node (ref J3) (pin 31)))
(net (code 46) (name A8)
(node (ref U1) (pin 25))
(node (ref J3) (pin 8)))
(node (ref J3) (pin 8))
(node (ref U1) (pin 25)))
(net (code 47) (name D3)
(node (ref U1) (pin 15))
(node (ref J3) (pin 30)))
(node (ref J3) (pin 30))
(node (ref U1) (pin 15)))
(net (code 48) (name A9)
(node (ref J3) (pin 7))
(node (ref U1) (pin 24)))

8
RC6502 RAM/RC6502 RAM.pro
View File

@ -1,4 +1,4 @@
update=25/12/2018 17:42:57
update=16/02/2019 22:23:41
version=1
last_client=kicad
[pcbnew]
@ -57,15 +57,15 @@ LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=D:/ownCloud/Documents/Projects/RC6502/Templates/rc6502_backplane
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=D:/ownCloud/Documents/Projects/RC6502/RC6502 RAM/export/
PlotDirectoryName=export/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[general]
version=1

176
RC6502 RAM/RC6502 RAM.sch
View File

@ -513,17 +513,6 @@ Wire Wire Line
2125 5200 2050 5200
Wire Wire Line
2125 5125 2125 5200
$Comp
L 74LS02 U3
U 1 1 5C1DAB94
P 2125 4175
F 0 "U3" H 2125 4225 50 0000 C CNN
F 1 "74LS02" H 2175 4125 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 2125 4175 50 0001 C CNN
F 3 "" H 2125 4175 50 0001 C CNN
1 2125 4175
0 -1 -1 0
$EndComp
Wire Wire Line
1800 5100 1800 4850
Wire Wire Line
@ -592,17 +581,6 @@ Wire Wire Line
2975 5750 2900 5750
Wire Wire Line
2975 5675 2975 5750
$Comp
L 74LS02 U3
U 2 1 5C1DB812
P 2975 4725
F 0 "U3" H 2975 4775 50 0000 C CNN
F 1 "74LS02" H 3025 4675 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 2975 4725 50 0001 C CNN
F 3 "" H 2975 4725 50 0001 C CNN
2 2975 4725
0 -1 -1 0
$EndComp
Wire Wire Line
2650 5650 2650 5400
Wire Wire Line
@ -671,17 +649,6 @@ Wire Wire Line
3800 6300 3725 6300
Wire Wire Line
3800 6225 3800 6300
$Comp
L 74LS02 U3
U 3 1 5C1DC564
P 3800 5275
F 0 "U3" H 3800 5325 50 0000 C CNN
F 1 "74LS02" H 3850 5225 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 3800 5275 50 0001 C CNN
F 3 "" H 3800 5275 50 0001 C CNN
3 3800 5275
0 -1 -1 0
$EndComp
Wire Wire Line
3475 6200 3475 5950
Wire Wire Line
@ -750,17 +717,6 @@ Wire Wire Line
4650 6850 4575 6850
Wire Wire Line
4650 6775 4650 6850
$Comp
L 74LS02 U3
U 4 1 5C1DC58E
P 4650 5825
F 0 "U3" H 4650 5875 50 0000 C CNN
F 1 "74LS02" H 4700 5775 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 4650 5825 50 0001 C CNN
F 3 "" H 4650 5825 50 0001 C CNN
4 4650 5825
0 -1 -1 0
$EndComp
Wire Wire Line
4325 6750 4325 6500
Wire Wire Line
@ -799,17 +755,6 @@ Wire Wire Line
4750 6425 4750 7025
Wire Wire Line
4325 6500 4550 6500
$Comp
L 74LS02 U4
U 1 1 5C1DE352
P 3650 3575
F 0 "U4" H 3650 3625 50 0000 C CNN
F 1 "74LS02" H 3700 3525 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 3650 3575 50 0001 C CNN
F 3 "" H 3650 3575 50 0001 C CNN
1 3650 3575
1 0 0 -1
$EndComp
Wire Wire Line
2125 3475 2125 3575
Wire Wire Line
@ -818,17 +763,6 @@ Wire Wire Line
2975 3675 3050 3675
Wire Wire Line
3050 3475 2125 3475
$Comp
L 74LS02 U4
U 2 1 5C1DF2B7
P 5325 4675
F 0 "U4" H 5325 4725 50 0000 C CNN
F 1 "74LS02" H 5375 4625 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 5325 4675 50 0001 C CNN
F 3 "" H 5325 4675 50 0001 C CNN
2 5325 4675
1 0 0 -1
$EndComp
Wire Wire Line
3800 4575 3800 4675
Wire Wire Line
@ -837,17 +771,6 @@ Wire Wire Line
4650 5225 4650 4775
Wire Wire Line
4650 4775 4725 4775
$Comp
L 74LS02 U4
U 3 1 5C1DFD68
P 6675 4125
F 0 "U4" H 6675 4175 50 0000 C CNN
F 1 "74LS02" H 6725 4075 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 6675 4125 50 0001 C CNN
F 3 "" H 6675 4125 50 0001 C CNN
3 6675 4125
1 0 0 -1
$EndComp
Wire Wire Line
5925 4675 6000 4675
Wire Wire Line
@ -910,17 +833,6 @@ Wire Wire Line
Connection ~ 10250 875
Connection ~ 9650 875
$Comp
L 74LS02 U4
U 4 1 5C1E36AB
P 6600 6750
F 0 "U4" H 6600 6800 50 0000 C CNN
F 1 "74LS02" H 6650 6700 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 6600 6750 50 0001 C CNN
F 3 "" H 6600 6750 50 0001 C CNN
4 6600 6750
0 -1 -1 0
$EndComp
$Comp
L GND #PWR015
U 1 1 5C1E3B47
P 6600 7500
@ -989,4 +901,92 @@ Wire Wire Line
Connection ~ 5100 1325
Text Notes 7025 6775 0 60 ~ 0
Enhanced RAM board with added support for ROM ICs of type 28C64 or 28C256, can be\naddressed high/low. Individual 4k blocks can be enabled via jumpers.
$Comp
L 74LS08 U3
U 1 1 5C68602F
P 2125 4175
F 0 "U3" H 2125 4225 50 0000 C CNN
F 1 "74LS08" H 2125 4125 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 2125 4175 50 0001 C CNN
F 3 "" H 2125 4175 50 0001 C CNN
1 2125 4175
0 -1 -1 0
$EndComp
$Comp
L 74LS08 U3
U 2 1 5C6865C4
P 2975 4725
F 0 "U3" H 2975 4775 50 0000 C CNN
F 1 "74LS08" H 2975 4675 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 2975 4725 50 0001 C CNN
F 3 "" H 2975 4725 50 0001 C CNN
2 2975 4725
0 -1 -1 0
$EndComp
$Comp
L 74LS08 U3
U 3 1 5C686812
P 3800 5275
F 0 "U3" H 3800 5325 50 0000 C CNN
F 1 "74LS08" H 3800 5225 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 3800 5275 50 0001 C CNN
F 3 "" H 3800 5275 50 0001 C CNN
3 3800 5275
0 -1 -1 0
$EndComp
$Comp
L 74LS08 U3
U 4 1 5C68689D
P 4650 5825
F 0 "U3" H 4650 5875 50 0000 C CNN
F 1 "74LS08" H 4650 5775 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 4650 5825 50 0001 C CNN
F 3 "" H 4650 5825 50 0001 C CNN
4 4650 5825
0 -1 -1 0
$EndComp
$Comp
L 74LS08 U4
U 1 1 5C687BF2
P 3650 3575
F 0 "U4" H 3650 3625 50 0000 C CNN
F 1 "74LS08" H 3650 3525 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 3650 3575 50 0001 C CNN
F 3 "" H 3650 3575 50 0001 C CNN
1 3650 3575
1 0 0 -1
$EndComp
$Comp
L 74LS08 U4
U 2 1 5C687CAF
P 5325 4675
F 0 "U4" H 5325 4725 50 0000 C CNN
F 1 "74LS08" H 5325 4625 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 5325 4675 50 0001 C CNN
F 3 "" H 5325 4675 50 0001 C CNN
2 5325 4675
1 0 0 -1
$EndComp
$Comp
L 74LS08 U4
U 3 1 5C687D29
P 6675 4125
F 0 "U4" H 6675 4175 50 0000 C CNN
F 1 "74LS08" H 6675 4075 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 6675 4125 50 0001 C CNN
F 3 "" H 6675 4125 50 0001 C CNN
3 6675 4125
1 0 0 -1
$EndComp
$Comp
L 74LS08 U4
U 4 1 5C687DB2
P 6600 6750
F 0 "U4" H 6600 6800 50 0000 C CNN
F 1 "74LS08" H 6600 6700 50 0000 C CNN
F 2 "Housings_DIP:DIP-14_W7.62mm_Socket" H 6600 6750 50 0001 C CNN
F 3 "" H 6600 6750 50 0001 C CNN
4 6600 6750
0 -1 -1 0
$EndComp
$EndSCHEMATC

949
RC6502 RAM/export/RC6502 RAM-B.Cu.gbl
View File

File diff suppressed because it is too large Load Diff

50
RC6502 RAM/export/RC6502 RAM-B.Mask.gbs
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Soldermask,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.7) date 12/22/18 18:54:53*
G04 Created by KiCad (PCBNEW 4.0.7) date 02/16/19 22:22:25*
%MOMM*%
%LPD*%
G01*
@ -166,6 +166,30 @@ X132715000Y-119380000D03*
X125095000Y-134620000D03*
X132715000Y-116840000D03*
D11*
X90805000Y-116840000D03*
D12*
X98425000Y-132080000D03*
X90805000Y-119380000D03*
X98425000Y-129540000D03*
X90805000Y-121920000D03*
X98425000Y-127000000D03*
X90805000Y-124460000D03*
X98425000Y-124460000D03*
X90805000Y-127000000D03*
X98425000Y-121920000D03*
X90805000Y-129540000D03*
X98425000Y-119380000D03*
X90805000Y-132080000D03*
X98425000Y-116840000D03*
D13*
X97155000Y-113030000D03*
X92155000Y-113030000D03*
D14*
X93345000Y-97790000D03*
D15*
X93345000Y-100330000D03*
X93345000Y-102870000D03*
D11*
X113665000Y-116840000D03*
D12*
X121285000Y-132080000D03*
@ -197,28 +221,4 @@ X102235000Y-129540000D03*
X109855000Y-119380000D03*
X102235000Y-132080000D03*
X109855000Y-116840000D03*
D11*
X90805000Y-116840000D03*
D12*
X98425000Y-132080000D03*
X90805000Y-119380000D03*
X98425000Y-129540000D03*
X90805000Y-121920000D03*
X98425000Y-127000000D03*
X90805000Y-124460000D03*
X98425000Y-124460000D03*
X90805000Y-127000000D03*
X98425000Y-121920000D03*
X90805000Y-129540000D03*
X98425000Y-119380000D03*
X90805000Y-132080000D03*
X98425000Y-116840000D03*
D13*
X97155000Y-113030000D03*
X92155000Y-113030000D03*
D14*
X93345000Y-97790000D03*
D15*
X93345000Y-100330000D03*
X93345000Y-102870000D03*
M02*

2
RC6502 RAM/export/RC6502 RAM-B.Paste.gbp
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Paste,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.7) date 12/22/18 18:54:53*
G04 Created by KiCad (PCBNEW 4.0.7) date 02/16/19 22:22:25*
%MOMM*%
%LPD*%
G01*

2
RC6502 RAM/export/RC6502 RAM-B.SilkS.gbo
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Legend,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.7) date 12/22/18 18:54:53*
G04 Created by KiCad (PCBNEW 4.0.7) date 02/16/19 22:22:25*
%MOMM*%
%LPD*%
G01*

2
RC6502 RAM/export/RC6502 RAM-Dwgs.User.gbr
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Drawing*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.7) date 12/22/18 18:54:53*
G04 Created by KiCad (PCBNEW 4.0.7) date 02/16/19 22:22:25*
%MOMM*%
%LPD*%
G01*

2
RC6502 RAM/export/RC6502 RAM-Edge.Cuts.gm1
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.7) date 12/22/18 18:54:53*
G04 Created by KiCad (PCBNEW 4.0.7) date 02/16/19 22:22:25*
%MOMM*%
%LPD*%
G01*

601
RC6502 RAM/export/RC6502 RAM-F.Cu.gtl
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Copper,L1,Top,Signal*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.7) date 12/22/18 18:54:53*
G04 Created by KiCad (PCBNEW 4.0.7) date 02/16/19 22:22:25*
%MOMM*%
%LPD*%
G01*
@ -168,6 +168,30 @@ X132715000Y-119380000D03*
X125095000Y-134620000D03*
X132715000Y-116840000D03*
D11*
X90805000Y-116840000D03*
D12*
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@ -199,30 +223,6 @@ X102235000Y-129540000D03*
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D14*
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D15*
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D16*
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@ -276,7 +276,6 @@ X142875000Y-108585000D03*
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50
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2
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491
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M02*

13
RC6502 RAM/export/RC6502 RAM.drl
View File

@ -1,5 +1,5 @@
M48
;DRILL file {KiCad 4.0.7} date 12/22/18 18:54:56
;DRILL file {KiCad 4.0.7} date 02/16/19 22:22:28
;FORMAT={2:4/ absolute / inch / suppress leading zeros}
FMAT,2
INCH,TZ
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RC6502 RAM/export/RC6502 RAM.pdf
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