Apple-1-HW
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RC6502-Apple-1-Replica
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Updated exports before sending to fabrication.

This commit is contained in:
Unknown 2017-06-20 00:21:20 +02:00
parent bc6eb09231
commit bd0a3a0245
27 changed files with 27 additions and 47 deletions
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2
RC6502 Apple 1 SBC/RC6502 Apple 1 SBC.pro
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@ -1,4 +1,4 @@
update=15/06/2017 16:01:54
update=20/06/2017 00:08:22
version=1
last_client=kicad
[pcbnew]

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-B.Cu.gbl
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Copper,L2,Bot,Signal*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-B.Mask.gbs
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Soldermask,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-B.Paste.gbp
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Paste,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-B.SilkS.gbo
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Legend,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-Dwgs.User.gbr
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Drawing*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-Edge.Cuts.gm1
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-F.Cu.gtl
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Copper,L1,Top,Signal*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-F.Mask.gts
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Soldermask,Top*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-F.Paste.gtp
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Paste,Top*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC-F.SilkS.gto
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Legend,Top*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/17/17 23:05:01*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:08:38*
%MOMM*%
%LPD*%
G01*

2
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC.drl
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@ -1,5 +1,5 @@
M48
;DRILL file {KiCad 4.0.6} date 06/17/17 23:05:05
;DRILL file {KiCad 4.0.6} date 06/20/17 00:08:41
;FORMAT={2:4/ absolute / inch / suppress leading zeros}
FMAT,2
INCH,TZ

BIN
RC6502 Apple 1 SBC/export/RC6502 Apple 1 SBC.pdf
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4
RC6502 Reset Circuit/Reset circuit.kicad_pcb
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@ -3,7 +3,7 @@
(general
(links 55)
(no_connects 0)
(area 92.634999 111.684999 191.845001 147.395001)
(area 90.735 110.15 195.938572 156.675001)
(thickness 1.6)
(drawings 35)
(tracks 160)
@ -87,7 +87,7 @@
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "D:/ownCloud/Documents/Projects/RC6502/RC6502 Reset Circuit/export/"))
(outputdirectory export/))
)
(net 0 "")

4
RC6502 Reset Circuit/Reset circuit.pro
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@ -1,4 +1,4 @@
update=10/06/2017 19:55:35
update=20/06/2017 00:10:34
version=1
last_client=kicad
[pcbnew]
@ -65,7 +65,7 @@ LibName33=C:/Program Files/KiCad/share/kicad/library/Oscillators
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=D:/ownCloud/Documents/Projects/RC6502/RC6502 Reset Circuit/export/
PlotDirectoryName=export/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew

2
RC6502 Reset Circuit/export/Reset circuit-B.Cu.gbl
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Copper,L2,Bot,Signal*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

2
RC6502 Reset Circuit/export/Reset circuit-B.Mask.gbs
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Soldermask,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

2
RC6502 Reset Circuit/export/Reset circuit-B.Paste.gbp
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Paste,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

2
RC6502 Reset Circuit/export/Reset circuit-B.SilkS.gbo
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Legend,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

2
RC6502 Reset Circuit/export/Reset circuit-Dwgs.User.gbr
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Drawing*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

2
RC6502 Reset Circuit/export/Reset circuit-Edge.Cuts.gm1
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

2
RC6502 Reset Circuit/export/Reset circuit-F.Cu.gtl
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Copper,L1,Top,Signal*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

2
RC6502 Reset Circuit/export/Reset circuit-F.Mask.gts
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Soldermask,Top*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

2
RC6502 Reset Circuit/export/Reset circuit-F.Paste.gtp
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Paste,Top*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*

22
RC6502 Reset Circuit/export/Reset circuit-F.SilkS.gto
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@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Legend,Top*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 19:53:39*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/20/17 00:11:08*
%MOMM*%
%LPD*%
G01*
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X182078334Y-124277381D02*
X181745000Y-123801190D01*
X181506905Y-124277381D02*

2
RC6502 Reset Circuit/export/Reset circuit.drl
View File

@ -1,5 +1,5 @@
M48
;DRILL file {KiCad 4.0.6} date 06/10/17 19:53:42
;DRILL file {KiCad 4.0.6} date 06/20/17 00:11:12
;FORMAT={2:4/ absolute / inch / suppress leading zeros}
FMAT,2
INCH,TZ

BIN
RC6502 Reset Circuit/export/Reset circuit.pdf
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