ca65 V2.15 - Git a85ac88 Main file : firmware.s65 Current file: firmware.s65 000000r 1 .setcpu "65c02" 000000r 1 .include "macros.inc65" 000000r 2 ; Push A and X, destroys A 000000r 2 .macro phax 000000r 2 pha 000000r 2 txa 000000r 2 pha 000000r 2 .endmacro 000000r 2 000000r 2 ; Push A and Y, destroys A 000000r 2 .macro phay 000000r 2 pha 000000r 2 tya 000000r 2 pha 000000r 2 .endmacro 000000r 2 000000r 2 ; Push A, X and Y, destroys A 000000r 2 .macro phaxy 000000r 2 pha 000000r 2 txa 000000r 2 pha 000000r 2 tya 000000r 2 pha 000000r 2 .endmacro 000000r 2 000000r 2 ; Pull A and X 000000r 2 .macro plax 000000r 2 pla 000000r 2 tax 000000r 2 pla 000000r 2 .endmacro 000000r 2 000000r 2 ; Pull A and Y 000000r 2 .macro play 000000r 2 pla 000000r 2 tay 000000r 2 pla 000000r 2 .endmacro 000000r 2 000000r 2 ; Pull A, X and Y 000000r 2 .macro plaxy 000000r 2 pla 000000r 2 tay 000000r 2 pla 000000r 2 tax 000000r 2 pla 000000r 2 .endmacro 000000r 2 000000r 2 ; Load zero page register reg/reg+1 with the 16-bit value, destroys A 000000r 2 .macro ld16 reg, value 000000r 2 lda #<(value) 000000r 2 sta reg 000000r 2 lda #>(value) 000000r 2 sta reg + 1 000000r 2 .endmacro 000000r 2 000000r 1 000000r 1 .include "io.inc65" 000000r 2 ; CPU frequency 000000r 2 000000r 2 F_CPU = 1000000 000000r 2 000000r 2 ; ACIA registers 000000r 2 000000r 2 ACIA_BASE = $7f00 000000r 2 ACIA_DATA = ACIA_BASE 000000r 2 ACIA_STATUS = ACIA_BASE + 1 000000r 2 ACIA_COMMAND = ACIA_BASE + 2 000000r 2 ACIA_CONTROL = ACIA_BASE + 3 000000r 2 000000r 2 ; ACIA control register bit values 000000r 2 000000r 2 ACIA_STOP_BITS_1 = %00000000 000000r 2 ACIA_STOP_BITS_2 = %10000000 000000r 2 ACIA_DATA_BITS_8 = %00000000 000000r 2 ACIA_DATA_BITS_7 = %00100000 000000r 2 ACIA_DATA_BITS_6 = %01000000 000000r 2 ACIA_DATA_BITS_5 = %01100000 000000r 2 ACIA_CLOCK_EXT = %00000000 000000r 2 ACIA_CLOCK_INT = %00010000 000000r 2 ACIA_BAUD_16XEXT = %00000000 000000r 2 ACIA_BAUD_50 = %00000001 000000r 2 ACIA_BAUD_75 = %00000010 000000r 2 ACIA_BAUD_109 = %00000011 000000r 2 ACIA_BAUD_134 = %00000100 000000r 2 ACIA_BAUD_150 = %00000101 000000r 2 ACIA_BAUD_300 = %00000110 000000r 2 ACIA_BAUD_600 = %00000111 000000r 2 ACIA_BAUD_1200 = %00001000 000000r 2 ACIA_BAUD_1800 = %00001001 000000r 2 ACIA_BAUD_2400 = %00001010 000000r 2 ACIA_BAUD_3600 = %00001011 000000r 2 ACIA_BAUD_4800 = %00001100 000000r 2 ACIA_BAUD_7200 = %00001101 000000r 2 ACIA_BAUD_9600 = %00001110 000000r 2 ACIA_BAUD_19200 = %00001111 000000r 2 000000r 2 ; ACIA command register bit values 000000r 2 000000r 2 ACIA_PARITY_ODD = %00000000 000000r 2 ACIA_PARITY_EVEN = %01000000 000000r 2 ACIA_PARITY_MARK = %10000000 000000r 2 ACIA_PARITY_SPACE = %11000000 000000r 2 ACIA_PARITY_DISABLE = %00000000 000000r 2 ACIA_PARITY_ENABLE = %00100000 000000r 2 ACIA_ECHO_DISABLE = %00000000 000000r 2 ACIA_ECHO_ENABLE = %00010000 000000r 2 ACIA_TX_INT_DISABLE_RTS_HIGH = %00000000 000000r 2 ACIA_TX_INT_ENABLE_RTS_LOW = %00000100 000000r 2 ACIA_TX_INT_DISABLE_RTS_LOW = %00001000 000000r 2 ACIA_TX_INT_DISABLE_BREAK = %00001100 000000r 2 ACIA_RX_INT_ENABLE = %00000000 000000r 2 ACIA_RX_INT_DISABLE = %00000010 000000r 2 ACIA_DTR_HIGH = %00000000 000000r 2 ACIA_DTR_LOW = %00000001 000000r 2 000000r 2 ; ACIA status register bit masks 000000r 2 000000r 2 ACIA_STATUS_IRQ = 1 << 7 000000r 2 ACIA_STATUS_DSR = 1 << 6 000000r 2 ACIA_STATUS_DCD = 1 << 5 000000r 2 ACIA_STATUS_TX_EMPTY = 1 << 4 000000r 2 ACIA_STATUS_RX_FULL = 1 << 3 000000r 2 ACIA_STATUS_OVERRUN = 1 << 2 000000r 2 ACIA_STATUS_FRAME_ERR = 1 << 1 000000r 2 ACIA_STATUS_PARITY_ERR = 1 << 0 000000r 2 000000r 2 ; VIA registers 000000r 2 000000r 2 VIA1_BASE = $8020 000000r 2 VIA1_ORB = VIA1_BASE 000000r 2 VIA1_IRB = VIA1_BASE 000000r 2 VIA1_ORA = VIA1_BASE + 1 000000r 2 VIA1_IRA = VIA1_BASE + 1 000000r 2 VIA1_DDRB = VIA1_BASE + 2 000000r 2 VIA1_DDRA = VIA1_BASE + 3 000000r 2 VIA1_T1C_L = VIA1_BASE + 4 000000r 2 VIA1_T1C_H = VIA1_BASE + 5 000000r 2 VIA1_T1L_L = VIA1_BASE + 6 000000r 2 VIA1_T1L_H = VIA1_BASE + 7 000000r 2 VIA1_T2C_L = VIA1_BASE + 8 000000r 2 VIA1_T2C_H = VIA1_BASE + 9 000000r 2 VIA1_SR = VIA1_BASE + 10 000000r 2 VIA1_ACR = VIA1_BASE + 11 000000r 2 VIA1_PCR = VIA1_BASE + 12 000000r 2 VIA1_IFR = VIA1_BASE + 13 000000r 2 VIA1_IER = VIA1_BASE + 14 000000r 2 VIA1_ORA_NH = VIA1_BASE + 15 000000r 2 VIA1_IRA_NH = VIA1_BASE + 15 000000r 2 000000r 2 VIA2_BASE = $8120 000000r 2 VIA2_ORB = VIA2_BASE 000000r 2 VIA2_IRB = VIA2_BASE 000000r 2 VIA2_ORA = VIA2_BASE + 1 000000r 2 VIA2_IRA = VIA2_BASE + 1 000000r 2 VIA2_DDRB = VIA2_BASE + 2 000000r 2 VIA2_DDRA = VIA2_BASE + 3 000000r 2 VIA2_T1C_L = VIA2_BASE + 4 000000r 2 VIA2_T1C_H = VIA2_BASE + 5 000000r 2 VIA2_T1L_L = VIA2_BASE + 6 000000r 2 VIA2_T1L_H = VIA2_BASE + 7 000000r 2 VIA2_T2C_L = VIA2_BASE + 8 000000r 2 VIA2_T2C_H = VIA2_BASE + 9 000000r 2 VIA2_SR = VIA2_BASE + 10 000000r 2 VIA2_ACR = VIA2_BASE + 11 000000r 2 VIA2_PCR = VIA2_BASE + 12 000000r 2 VIA2_IFR = VIA2_BASE + 13 000000r 2 VIA2_IER = VIA2_BASE + 14 000000r 2 VIA2_ORA_NH = VIA2_BASE + 15 000000r 2 VIA2_IRA_NH = VIA2_BASE + 15 000000r 2 000000r 2 ; Port bits 000000r 2 000000r 2 VIA_PA0 = (1 << 0) 000000r 2 VIA_PA1 = (1 << 1) 000000r 2 VIA_PA2 = (1 << 2) 000000r 2 VIA_PA3 = (1 << 3) 000000r 2 VIA_PA4 = (1 << 4) 000000r 2 VIA_PA5 = (1 << 5) 000000r 2 VIA_PA6 = (1 << 6) 000000r 2 VIA_PA7 = (1 << 7) 000000r 2 000000r 2 ; Port bits 000000r 2 000000r 2 VIA_PB0 = 1 << 0 000000r 2 VIA_PB1 = 1 << 1 000000r 2 VIA_PB2 = 1 << 2 000000r 2 VIA_PB3 = 1 << 3 000000r 2 VIA_PB4 = 1 << 4 000000r 2 VIA_PB5 = 1 << 5 000000r 2 VIA_PB6 = 1 << 6 000000r 2 VIA_PB7 = 1 << 7 000000r 2 000000r 1 000000r 1 .segment "VECTORS" 000000r 1 000000r 1 rr rr .word nmi 000002r 1 rr rr .word reset 000004r 1 rr rr .word irq 000006r 1 000006r 1 .code 000000r 1 000000r 1 4C rr rr reset: jmp main 000003r 1 000003r 1 40 nmi: rti 000004r 1 000004r 1 40 irq: rti 000005r 1 000005r 1 main: 000005r 1 000005r 1 4C rr rr jmp lcd_init2 000008r 1 000008r 1 000008r 1 loop: 000008r 1 000008r 1 4C rr rr jmp loop 00000Br 1 lcd_init2: 00000Br 1 A9 FF lda #$ff 00000Dr 1 8D 21 81 sta VIA2_ORA 000010r 1 8D 23 81 sta VIA2_DDRA 000013r 1 A2 32 ldx #50 000015r 1 20 rr rr jsr delay_ms 000018r 1 000018r 1 ;set register select bit to 0 for command/control 000018r 1 000018r 1 ;start init sequence 000018r 1 A9 03 lda #$03 00001Ar 1 20 rr rr jsr strobe_enable 00001Dr 1 A2 05 ldx #5 00001Fr 1 20 rr rr jsr delay_ms 000022r 1 000022r 1 A9 03 lda #$03 000024r 1 20 rr rr jsr strobe_enable 000027r 1 A2 05 ldx #5 000029r 1 20 rr rr jsr delay_ms 00002Cr 1 00002Cr 1 A9 03 lda #$03 00002Er 1 20 rr rr jsr strobe_enable 000031r 1 A2 05 ldx #5 000033r 1 20 rr rr jsr delay_ms 000036r 1 000036r 1 A9 02 lda #$02 000038r 1 20 rr rr jsr strobe_enable 00003Br 1 A2 03 ldx #3 00003Dr 1 20 rr rr jsr delay_ms 000040r 1 000040r 1 ;now in 4 bit mode 000040r 1 000040r 1 ;function set 000040r 1 A9 02 lda #$02 ;set data length to 4 bits 000042r 1 20 rr rr jsr strobe_enable 000045r 1 000045r 1 000045r 1 ;no delay needed here 000045r 1 000045r 1 000045r 1 A9 08 lda #$08 ;2 lines 5x8 pixels 000047r 1 20 rr rr jsr strobe_enable 00004Ar 1 A2 03 ldx #3 00004Cr 1 20 rr rr jsr delay_ms 00004Fr 1 00004Fr 1 A9 00 lda #$00 ;turn display off 000051r 1 20 rr rr jsr strobe_enable 000054r 1 A9 08 lda #$08 000056r 1 20 rr rr jsr strobe_enable 000059r 1 A2 03 ldx #3 00005Br 1 20 rr rr jsr delay_ms 00005Er 1 00005Er 1 A9 00 lda #$00 ;clear display 000060r 1 20 rr rr jsr strobe_enable 000063r 1 A9 01 lda #$01 000065r 1 20 rr rr jsr strobe_enable 000068r 1 A2 03 ldx #3 00006Ar 1 20 rr rr jsr delay_ms 00006Dr 1 00006Dr 1 A9 00 lda #$00 ;entry mode set 00006Fr 1 20 rr rr jsr strobe_enable 000072r 1 A9 06 lda #$06 000074r 1 20 rr rr jsr strobe_enable 000077r 1 A2 03 ldx #3 000079r 1 20 rr rr jsr delay_ms 00007Cr 1 ;end of initialization 00007Cr 1 00007Cr 1 A9 00 lda #$00 ;turn display on 00007Er 1 20 rr rr jsr strobe_enable 000081r 1 A9 0F lda #$0f ;display on, cursor on, blink on 000083r 1 20 rr rr jsr strobe_enable 000086r 1 A2 03 ldx #3 000088r 1 20 rr rr jsr delay_ms 00008Br 1 00008Br 1 A9 00 lda #$00 ;CURSOR HOME 00008Dr 1 20 rr rr jsr strobe_enable 000090r 1 A9 02 lda #$02 ;cursor home 000092r 1 20 rr rr jsr strobe_enable 000095r 1 A2 03 ldx #3 000097r 1 20 rr rr jsr delay_ms 00009Ar 1 00009Ar 1 4C rr rr jmp write_hello_world 00009Dr 1 00009Dr 1 write_hello_world: 00009Dr 1 ;send H 00009Dr 1 A9 14 lda #$14 00009Fr 1 20 rr rr jsr strobe_enable 0000A2r 1 A2 05 ldx #5 0000A4r 1 20 rr rr jsr delay_ms 0000A7r 1 0000A7r 1 A9 18 lda #$18 0000A9r 1 20 rr rr jsr strobe_enable 0000ACr 1 A2 05 ldx #5 0000AEr 1 20 rr rr jsr delay_ms 0000B1r 1 0000B1r 1 ;send E 0000B1r 1 A9 14 lda #$14 0000B3r 1 20 rr rr jsr strobe_enable 0000B6r 1 A2 05 ldx #5 0000B8r 1 20 rr rr jsr delay_ms 0000BBr 1 0000BBr 1 A9 15 lda #$15 0000BDr 1 20 rr rr jsr strobe_enable 0000C0r 1 A2 05 ldx #5 0000C2r 1 20 rr rr jsr delay_ms 0000C5r 1 0000C5r 1 ;add in extra strobe for reading 8 status bits 0000C5r 1 A9 00 lda #00 0000C7r 1 20 rr rr jsr strobe_enable 0000CAr 1 A9 00 lda #00 0000CCr 1 20 rr rr jsr strobe_enable 0000CFr 1 0000CFr 1 ;send L 0000CFr 1 A9 14 lda #$14 0000D1r 1 20 rr rr jsr strobe_enable 0000D4r 1 A2 05 ldx #5 0000D6r 1 20 rr rr jsr delay_ms 0000D9r 1 0000D9r 1 A9 1C lda #$1C 0000DBr 1 20 rr rr jsr strobe_enable 0000DEr 1 A2 05 ldx #5 0000E0r 1 20 rr rr jsr delay_ms 0000E3r 1 0000E3r 1 ;send L 0000E3r 1 A9 14 lda #$14 0000E5r 1 20 rr rr jsr strobe_enable 0000E8r 1 A2 05 ldx #5 0000EAr 1 20 rr rr jsr delay_ms 0000EDr 1 0000EDr 1 A9 1C lda #$1C 0000EFr 1 20 rr rr jsr strobe_enable 0000F2r 1 A2 05 ldx #5 0000F4r 1 20 rr rr jsr delay_ms 0000F7r 1 0000F7r 1 ;send O 0000F7r 1 A9 14 lda #$14 0000F9r 1 20 rr rr jsr strobe_enable 0000FCr 1 A2 05 ldx #5 0000FEr 1 20 rr rr jsr delay_ms 000101r 1 000101r 1 A9 1F lda #$1F 000103r 1 20 rr rr jsr strobe_enable 000106r 1 A2 05 ldx #5 000108r 1 20 rr rr jsr delay_ms 00010Br 1 00010Br 1 ;send space 00010Br 1 A9 12 lda #$12 00010Dr 1 20 rr rr jsr strobe_enable 000110r 1 A2 05 ldx #5 000112r 1 20 rr rr jsr delay_ms 000115r 1 000115r 1 A9 10 lda #$10 000117r 1 20 rr rr jsr strobe_enable 00011Ar 1 A2 05 ldx #5 00011Cr 1 20 rr rr jsr delay_ms 00011Fr 1 00011Fr 1 ;send W 00011Fr 1 A9 15 lda #$15 000121r 1 20 rr rr jsr strobe_enable 000124r 1 A2 05 ldx #5 000126r 1 20 rr rr jsr delay_ms 000129r 1 000129r 1 A9 17 lda #$17 00012Br 1 20 rr rr jsr strobe_enable 00012Er 1 A2 05 ldx #5 000130r 1 20 rr rr jsr delay_ms 000133r 1 000133r 1 ;send O 000133r 1 A9 14 lda #$14 000135r 1 20 rr rr jsr strobe_enable 000138r 1 A2 05 ldx #5 00013Ar 1 20 rr rr jsr delay_ms 00013Dr 1 00013Dr 1 A9 1F lda #$1F 00013Fr 1 20 rr rr jsr strobe_enable 000142r 1 A2 05 ldx #5 000144r 1 20 rr rr jsr delay_ms 000147r 1 000147r 1 ;send R 000147r 1 A9 15 lda #$15 000149r 1 20 rr rr jsr strobe_enable 00014Cr 1 A2 05 ldx #5 00014Er 1 20 rr rr jsr delay_ms 000151r 1 000151r 1 A9 12 lda #$12 000153r 1 20 rr rr jsr strobe_enable 000156r 1 A2 05 ldx #5 000158r 1 20 rr rr jsr delay_ms 00015Br 1 00015Br 1 ;send L 00015Br 1 A9 14 lda #$14 00015Dr 1 20 rr rr jsr strobe_enable 000160r 1 A2 05 ldx #5 000162r 1 20 rr rr jsr delay_ms 000165r 1 000165r 1 A9 1C lda #$1C 000167r 1 20 rr rr jsr strobe_enable 00016Ar 1 A2 05 ldx #5 00016Cr 1 20 rr rr jsr delay_ms 00016Fr 1 00016Fr 1 ;send D 00016Fr 1 A9 14 lda #$14 000171r 1 20 rr rr jsr strobe_enable 000174r 1 A2 05 ldx #5 000176r 1 20 rr rr jsr delay_ms 000179r 1 000179r 1 A9 14 lda #$14 00017Br 1 20 rr rr jsr strobe_enable 00017Er 1 A2 05 ldx #5 000180r 1 20 rr rr jsr delay_ms 000183r 1 000183r 1 ;send ! 000183r 1 A9 12 lda #$12 000185r 1 20 rr rr jsr strobe_enable 000188r 1 A2 05 ldx #5 00018Ar 1 20 rr rr jsr delay_ms 00018Dr 1 00018Dr 1 A9 11 lda #$11 00018Fr 1 20 rr rr jsr strobe_enable 000192r 1 A2 05 ldx #5 000194r 1 20 rr rr jsr delay_ms 000197r 1 000197r 1 4C rr rr jmp loop 00019Ar 1 00019Ar 1 strobe_enable: 00019Ar 1 09 20 ora #$20 ;add enable bit 00019Cr 1 8D 21 81 sta VIA2_ORA ;send value out to via 00019Fr 1 A2 0A ldx #10 0001A1r 1 20 rr rr jsr delay_ms 0001A4r 1 29 DF and #$DF ;mask to take out enable 0001A6r 1 8D 21 81 sta VIA2_ORA ;take out enable bit and send to via 0001A9r 1 0001A9r 1 60 rts 0001AAr 1 0001AAr 1 ; Delay the number of miliseconds specified by X 0001AAr 1 ; This is hardcoded for a 1 MHz system clock 0001AAr 1 48 delay_ms: pha ; 3 0001ABr 1 8A txa ; 2 0001ACr 1 48 pha ; 3 0001ADr 1 98 tya ; 2 0001AEr 1 48 pha ; 3 0001AFr 1 0001AFr 1 A4 00 ldy $00 ; 3 (dummy operation) 0001B1r 1 A0 BE ldy #190 ; 2 0001B3r 1 88 @loop1: dey ; 190 * 2 0001B4r 1 D0 FD bne @loop1 ; 190 * 3 - 1 0001B6r 1 0001B6r 1 CA @loop2: dex ; 2 0001B7r 1 F0 09 beq @return ; (x - 1) * 2 + 3 0001B9r 1 0001B9r 1 EA nop ; 2 0001BAr 1 A0 C6 ldy #198 ; 2 0001BCr 1 88 @loop3: dey ; 198 * 2 0001BDr 1 D0 FD bne @loop3 ; 198 * 3 - 1 0001BFr 1 0001BFr 1 4C rr rr jmp @loop2 ; 3 0001C2r 1 0001C2r 1 68 @return: pla ; 4 0001C3r 1 A8 tay ; 2 0001C4r 1 68 pla ; 4 0001C5r 1 AA tax ; 2 0001C6r 1 68 pla ; 4 0001C7r 1 60 rts ; 6 (+ 6 for JSR) 0001C7r 1