; CPU frequency

F_CPU = 1000000

; ACIA registers

ACIA_BASE    = $7f00
ACIA_DATA    = ACIA_BASE
ACIA_STATUS  = ACIA_BASE + 1
ACIA_COMMAND = ACIA_BASE + 2
ACIA_CONTROL = ACIA_BASE + 3

; ACIA control register bit values

ACIA_STOP_BITS_1 = %00000000
ACIA_STOP_BITS_2 = %10000000
ACIA_DATA_BITS_8 = %00000000
ACIA_DATA_BITS_7 = %00100000
ACIA_DATA_BITS_6 = %01000000
ACIA_DATA_BITS_5 = %01100000
ACIA_CLOCK_EXT   = %00000000
ACIA_CLOCK_INT   = %00010000
ACIA_BAUD_16XEXT = %00000000
ACIA_BAUD_50     = %00000001
ACIA_BAUD_75     = %00000010
ACIA_BAUD_109    = %00000011
ACIA_BAUD_134    = %00000100
ACIA_BAUD_150    = %00000101
ACIA_BAUD_300    = %00000110
ACIA_BAUD_600    = %00000111
ACIA_BAUD_1200   = %00001000
ACIA_BAUD_1800   = %00001001
ACIA_BAUD_2400   = %00001010
ACIA_BAUD_3600   = %00001011
ACIA_BAUD_4800   = %00001100
ACIA_BAUD_7200   = %00001101
ACIA_BAUD_9600   = %00001110
ACIA_BAUD_19200  = %00001111

; ACIA command register bit values

ACIA_PARITY_ODD              = %00000000
ACIA_PARITY_EVEN             = %01000000
ACIA_PARITY_MARK             = %10000000
ACIA_PARITY_SPACE            = %11000000
ACIA_PARITY_DISABLE          = %00000000
ACIA_PARITY_ENABLE           = %00100000
ACIA_ECHO_DISABLE            = %00000000
ACIA_ECHO_ENABLE             = %00010000
ACIA_TX_INT_DISABLE_RTS_HIGH = %00000000
ACIA_TX_INT_ENABLE_RTS_LOW   = %00000100
ACIA_TX_INT_DISABLE_RTS_LOW  = %00001000
ACIA_TX_INT_DISABLE_BREAK    = %00001100
ACIA_RX_INT_ENABLE           = %00000000
ACIA_RX_INT_DISABLE          = %00000010
ACIA_DTR_HIGH                = %00000000
ACIA_DTR_LOW                 = %00000001

; ACIA status register bit masks

ACIA_STATUS_IRQ        = 1 << 7
ACIA_STATUS_DSR        = 1 << 6
ACIA_STATUS_DCD        = 1 << 5
ACIA_STATUS_TX_EMPTY   = 1 << 4
ACIA_STATUS_RX_FULL    = 1 << 3
ACIA_STATUS_OVERRUN    = 1 << 2
ACIA_STATUS_FRAME_ERR  = 1 << 1
ACIA_STATUS_PARITY_ERR = 1 << 0

; VIA registers

VIA1_BASE   = $8020
VIA1_ORB    = VIA1_BASE
VIA1_IRB    = VIA1_BASE
VIA1_ORA    = VIA1_BASE + 1
VIA1_IRA    = VIA1_BASE + 1
VIA1_DDRB   = VIA1_BASE + 2
VIA1_DDRA   = VIA1_BASE + 3
VIA1_T1C_L  = VIA1_BASE + 4
VIA1_T1C_H  = VIA1_BASE + 5
VIA1_T1L_L  = VIA1_BASE + 6
VIA1_T1L_H  = VIA1_BASE + 7
VIA1_T2C_L  = VIA1_BASE + 8
VIA1_T2C_H  = VIA1_BASE + 9
VIA1_SR     = VIA1_BASE + 10
VIA1_ACR    = VIA1_BASE + 11
VIA1_PCR    = VIA1_BASE + 12
VIA1_IFR    = VIA1_BASE + 13
VIA1_IER    = VIA1_BASE + 14
VIA1_ORA_NH = VIA1_BASE + 15
VIA1_IRA_NH = VIA1_BASE + 15

VIA2_BASE   = $8120
VIA2_ORB    = VIA2_BASE
VIA2_IRB    = VIA2_BASE
VIA2_ORA    = VIA2_BASE + 1
VIA2_IRA    = VIA2_BASE + 1
VIA2_DDRB   = VIA2_BASE + 2
VIA2_DDRA   = VIA2_BASE + 3
VIA2_T1C_L  = VIA2_BASE + 4
VIA2_T1C_H  = VIA2_BASE + 5
VIA2_T1L_L  = VIA2_BASE + 6
VIA2_T1L_H  = VIA2_BASE + 7
VIA2_T2C_L  = VIA2_BASE + 8
VIA2_T2C_H  = VIA2_BASE + 9
VIA2_SR     = VIA2_BASE + 10
VIA2_ACR    = VIA2_BASE + 11
VIA2_PCR    = VIA2_BASE + 12
VIA2_IFR    = VIA2_BASE + 13
VIA2_IER    = VIA2_BASE + 14
VIA2_ORA_NH = VIA2_BASE + 15
VIA2_IRA_NH = VIA2_BASE + 15

; Port bits

VIA_PA0 = (1 << 0)
VIA_PA1 = (1 << 1)
VIA_PA2 = (1 << 2)
VIA_PA3 = (1 << 3)
VIA_PA4 = (1 << 4)
VIA_PA5 = (1 << 5)
VIA_PA6 = (1 << 6)
VIA_PA7 = (1 << 7)

; Port bits

VIA_PB0 = 1 << 0
VIA_PB1 = 1 << 1
VIA_PB2 = 1 << 2
VIA_PB3 = 1 << 3
VIA_PB4 = 1 << 4
VIA_PB5 = 1 << 5
VIA_PB6 = 1 << 6
VIA_PB7 = 1 << 7