mirror of
https://github.com/jonthomasson/retro1.git
synced 2024-06-10 05:29:33 +00:00
338 lines
14 KiB
Plaintext
338 lines
14 KiB
Plaintext
ca65 V2.15 - Git f7cdfbf
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Main file : interrupt.s65
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Current file: interrupt.s65
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000000r 1 .include "zeropage.inc65"
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000000r 2 .globalzp sp
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000000r 2 .globalzp sreg
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000000r 2 .globalzp regsave
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000000r 2 .globalzp regbank
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000000r 2 .globalzp tmp1
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000000r 2 .globalzp tmp2
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000000r 2 .globalzp tmp3
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000000r 2 .globalzp tmp4
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000000r 2 .globalzp tmpstack
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000000r 2 .globalzp ptr1
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000000r 2 .globalzp ptr2
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000000r 2 .globalzp ptr3
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000000r 2 .globalzp ptr4
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000000r 2 .globalzp _millis
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000000r 2 .globalzp _jiffies
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000000r 2 .globalzp _seconds
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000000r 2 .globalzp _minutes
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000000r 2 .globalzp _hours
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000000r 2 .globalzp key_code
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000000r 2 .globalzp key_modifiers
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000000r 2 .globalzp key_tmp1
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000000r 2 .globalzp key_tmp2
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000000r 2 .globalzp lcd_enable_bits
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000000r 2 .globalzp lcd_cursor
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000000r 2 .globalzp lcd_row
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000000r 2 .globalzp lcd_column
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000000r 2 .globalzp _interrupted
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000000r 2
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000000r 1 .include "io.inc65"
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000000r 2 ; CPU frequency
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000000r 2
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000000r 2 F_CPU = 1000000
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000000r 2
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000000r 2 ; ACIA registers
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000000r 2
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000000r 2 ACIA_BASE = $A000
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000000r 2 ACIA_DATA = ACIA_BASE
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000000r 2 ACIA_STATUS = ACIA_BASE + 1
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000000r 2 ACIA_COMMAND = ACIA_BASE + 2
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000000r 2 ACIA_CONTROL = ACIA_BASE + 3
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000000r 2
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000000r 2 ; ACIA control register bit values
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000000r 2
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000000r 2 ACIA_STOP_BITS_1 = %00000000
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000000r 2 ACIA_STOP_BITS_2 = %10000000
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000000r 2 ACIA_DATA_BITS_8 = %00000000
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000000r 2 ACIA_DATA_BITS_7 = %00100000
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000000r 2 ACIA_DATA_BITS_6 = %01000000
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000000r 2 ACIA_DATA_BITS_5 = %01100000
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000000r 2 ACIA_CLOCK_EXT = %00000000
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000000r 2 ACIA_CLOCK_INT = %00010000
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000000r 2 ACIA_BAUD_16XEXT = %00000000
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000000r 2 ACIA_BAUD_50 = %00000001
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000000r 2 ACIA_BAUD_75 = %00000010
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000000r 2 ACIA_BAUD_109 = %00000011
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000000r 2 ACIA_BAUD_134 = %00000100
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000000r 2 ACIA_BAUD_150 = %00000101
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000000r 2 ACIA_BAUD_300 = %00000110
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000000r 2 ACIA_BAUD_600 = %00000111
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000000r 2 ACIA_BAUD_1200 = %00001000
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000000r 2 ACIA_BAUD_1800 = %00001001
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000000r 2 ACIA_BAUD_2400 = %00001010
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000000r 2 ACIA_BAUD_3600 = %00001011
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000000r 2 ACIA_BAUD_4800 = %00001100
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000000r 2 ACIA_BAUD_7200 = %00001101
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000000r 2 ACIA_BAUD_9600 = %00001110
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000000r 2 ACIA_BAUD_19200 = %00001111
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000000r 2
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000000r 2 ; ACIA command register bit values
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000000r 2
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000000r 2 ACIA_PARITY_ODD = %00000000
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000000r 2 ACIA_PARITY_EVEN = %01000000
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000000r 2 ACIA_PARITY_MARK = %10000000
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000000r 2 ACIA_PARITY_SPACE = %11000000
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000000r 2 ACIA_PARITY_DISABLE = %00000000
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000000r 2 ACIA_PARITY_ENABLE = %00100000
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000000r 2 ACIA_ECHO_DISABLE = %00000000
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000000r 2 ACIA_ECHO_ENABLE = %00010000
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000000r 2 ACIA_TX_INT_DISABLE_RTS_HIGH = %00000000
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000000r 2 ACIA_TX_INT_ENABLE_RTS_LOW = %00000100
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000000r 2 ACIA_TX_INT_DISABLE_RTS_LOW = %00001000
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000000r 2 ACIA_TX_INT_DISABLE_BREAK = %00001100
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000000r 2 ACIA_RX_INT_ENABLE = %00000000
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000000r 2 ACIA_RX_INT_DISABLE = %00000010
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000000r 2 ACIA_DTR_HIGH = %00000000
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000000r 2 ACIA_DTR_LOW = %00000001
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000000r 2
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000000r 2 ; ACIA status register bit masks
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000000r 2
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000000r 2 ACIA_STATUS_IRQ = 1 << 7
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000000r 2 ACIA_STATUS_DSR = 1 << 6
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000000r 2 ACIA_STATUS_DCD = 1 << 5
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000000r 2 ACIA_STATUS_TX_EMPTY = 1 << 4
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000000r 2 ACIA_STATUS_RX_FULL = 1 << 3
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000000r 2 ACIA_STATUS_OVERRUN = 1 << 2
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000000r 2 ACIA_STATUS_FRAME_ERR = 1 << 1
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000000r 2 ACIA_STATUS_PARITY_ERR = 1 << 0
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000000r 2
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000000r 2 ; VIA registers
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000000r 2
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000000r 2 VIA1_BASE = $8020
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000000r 2 VIA1_ORB = VIA1_BASE
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000000r 2 VIA1_IRB = VIA1_BASE
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000000r 2 VIA1_ORA = VIA1_BASE + 1
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000000r 2 VIA1_IRA = VIA1_BASE + 1
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000000r 2 VIA1_DDRB = VIA1_BASE + 2
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000000r 2 VIA1_DDRA = VIA1_BASE + 3
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000000r 2 VIA1_T1C_L = VIA1_BASE + 4
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000000r 2 VIA1_T1C_H = VIA1_BASE + 5
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000000r 2 VIA1_T1L_L = VIA1_BASE + 6
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000000r 2 VIA1_T1L_H = VIA1_BASE + 7
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000000r 2 VIA1_T2C_L = VIA1_BASE + 8
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000000r 2 VIA1_T2C_H = VIA1_BASE + 9
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000000r 2 VIA1_SR = VIA1_BASE + 10
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000000r 2 VIA1_ACR = VIA1_BASE + 11
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000000r 2 VIA1_PCR = VIA1_BASE + 12
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000000r 2 VIA1_IFR = VIA1_BASE + 13
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000000r 2 VIA1_IER = VIA1_BASE + 14
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000000r 2 VIA1_ORA_NH = VIA1_BASE + 15
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000000r 2 VIA1_IRA_NH = VIA1_BASE + 15
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000000r 2
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000000r 2 VIA2_BASE = $8120
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000000r 2 VIA2_ORB = VIA2_BASE
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000000r 2 VIA2_IRB = VIA2_BASE
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000000r 2 VIA2_ORA = VIA2_BASE + 1
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000000r 2 VIA2_IRA = VIA2_BASE + 1
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000000r 2 VIA2_DDRB = VIA2_BASE + 2
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000000r 2 VIA2_DDRA = VIA2_BASE + 3
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000000r 2 VIA2_T1C_L = VIA2_BASE + 4
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000000r 2 VIA2_T1C_H = VIA2_BASE + 5
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000000r 2 VIA2_T1L_L = VIA2_BASE + 6
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000000r 2 VIA2_T1L_H = VIA2_BASE + 7
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000000r 2 VIA2_T2C_L = VIA2_BASE + 8
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000000r 2 VIA2_T2C_H = VIA2_BASE + 9
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000000r 2 VIA2_SR = VIA2_BASE + 10
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000000r 2 VIA2_ACR = VIA2_BASE + 11
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000000r 2 VIA2_PCR = VIA2_BASE + 12
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000000r 2 VIA2_IFR = VIA2_BASE + 13
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000000r 2 VIA2_IER = VIA2_BASE + 14
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000000r 2 VIA2_ORA_NH = VIA2_BASE + 15
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000000r 2 VIA2_IRA_NH = VIA2_BASE + 15
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000000r 2
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000000r 2 ; Port bits
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000000r 2
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000000r 2 VIA_PA0 = (1 << 0)
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000000r 2 VIA_PA1 = (1 << 1)
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000000r 2 VIA_PA2 = (1 << 2)
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000000r 2 VIA_PA3 = (1 << 3)
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000000r 2 VIA_PA4 = (1 << 4)
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000000r 2 VIA_PA5 = (1 << 5)
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000000r 2 VIA_PA6 = (1 << 6)
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000000r 2 VIA_PA7 = (1 << 7)
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000000r 2
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000000r 2 ; Port bits
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000000r 2
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000000r 2 VIA_PB0 = 1 << 0
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000000r 2 VIA_PB1 = 1 << 1
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000000r 2 VIA_PB2 = 1 << 2
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000000r 2 VIA_PB3 = 1 << 3
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000000r 2 VIA_PB4 = 1 << 4
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000000r 2 VIA_PB5 = 1 << 5
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000000r 2 VIA_PB6 = 1 << 6
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000000r 2 VIA_PB7 = 1 << 7
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000000r 2
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000000r 2 ; SID registers
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000000r 2
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000000r 2 SID_BASE = $7f60
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000000r 2 SID_VOICE1_FREQ_L = SID_BASE
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000000r 2 SID_VOICE1_FREQ_H = SID_BASE + 1
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000000r 2 SID_VOICE1_PW_L = SID_BASE + 2
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000000r 2 SID_VOICE1_PW_H = SID_BASE + 3
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000000r 2 SID_VOICE1_CTRL = SID_BASE + 4
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000000r 2 SID_VOICE1_AD = SID_BASE + 5
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000000r 2 SID_VOICE1_SR = SID_BASE + 6
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000000r 2 SID_VOICE2_FREQ_L = SID_BASE + 7
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000000r 2 SID_VOICE2_FREQ_H = SID_BASE + 8
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000000r 2 SID_VOICE2_PW_L = SID_BASE + 9
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000000r 2 SID_VOICE2_PW_H = SID_BASE + 10
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000000r 2 SID_VOICE2_CTRL = SID_BASE + 11
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000000r 2 SID_VOICE2_AD = SID_BASE + 12
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000000r 2 SID_VOICE2_SR = SID_BASE + 13
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000000r 2 SID_VOICE3_FREQ_L = SID_BASE + 14
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000000r 2 SID_VOICE3_FREQ_H = SID_BASE + 15
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000000r 2 SID_VOICE3_PW_L = SID_BASE + 16
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000000r 2 SID_VOICE3_PW_H = SID_BASE + 17
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000000r 2 SID_VOICE3_CTRL = SID_BASE + 18
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000000r 2 SID_VOICE3_AD = SID_BASE + 19
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000000r 2 SID_VOICE3_SR = SID_BASE + 20
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000000r 2 SID_FC_L = SID_BASE + 21
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000000r 2 SID_FC_H = SID_BASE + 22
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000000r 2 SID_RES_FILT = SID_BASE + 23
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000000r 2 SID_MODE_VOLUME = SID_BASE + 24
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000000r 2 SID_POTX = SID_BASE + 25
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000000r 2 SID_POTY = SID_BASE + 26
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000000r 2 SID_OSC3 = SID_BASE + 27
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000000r 2 SID_ENV3 = SID_BASE + 28
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000000r 2
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000000r 2 ; LED
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000000r 2
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000000r 2 LED_DDR = VIA1_DDRA
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000000r 2 LED_OUT = VIA1_ORA
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000000r 2 LED = VIA_PA7
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000000r 2
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000000r 1 .include "macros.inc65"
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000000r 2 ; Push X
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000000r 2 .macro phx
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000000r 2 sta tmpstack
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000000r 2 txa
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000000r 2 pha
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Push Y
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000000r 2 .macro phy
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000000r 2 sta tmpstack
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000000r 2 tya
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000000r 2 pha
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Push X and Y
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000000r 2 .macro phxy
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000000r 2 sta tmpstack
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000000r 2 txa
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000000r 2 pha
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000000r 2 tya
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000000r 2 pha
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Push A and X
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000000r 2 .macro phax
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000000r 2 sta tmpstack
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000000r 2 pha
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000000r 2 txa
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000000r 2 pha
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Push A and Y
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000000r 2 .macro phay
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000000r 2 sta tmpstack
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000000r 2 pha
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000000r 2 tya
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000000r 2 pha
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Push A, X and Y
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000000r 2 .macro phaxy
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000000r 2 sta tmpstack
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000000r 2 pha
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000000r 2 txa
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000000r 2 pha
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000000r 2 tya
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000000r 2 pha
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull X
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000000r 2 .macro plx
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000000r 2 sta tmpstack
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000000r 2 pla
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000000r 2 tax
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull Y
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000000r 2 .macro ply
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000000r 2 sta tmpstack
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000000r 2 pla
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000000r 2 tay
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull X and Y
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000000r 2 .macro plxy
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000000r 2 sta tmpstack
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000000r 2 pla
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000000r 2 tay
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000000r 2 pla
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000000r 2 tax
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000000r 2 lda tmpstack
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull A and X
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000000r 2 .macro plax
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000000r 2 pla
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000000r 2 tax
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000000r 2 pla
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull A and Y
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000000r 2 .macro play
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000000r 2 pla
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000000r 2 tay
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000000r 2 pla
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull A, X and Y
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000000r 2 .macro plaxy
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000000r 2 pla
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000000r 2 tay
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000000r 2 pla
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000000r 2 tax
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000000r 2 pla
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Load zero page register reg/reg+1 with the 16-bit value, destroys A
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000000r 2 .macro ld16 reg, value
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000000r 2 lda #<(value)
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000000r 2 sta reg
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000000r 2 lda #>(value)
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000000r 2 sta reg + 1
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000000r 2 .endmacro
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000000r 2
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000000r 1
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000000r 1 .export nmi_handler
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000000r 1 .export irq_handler
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000000r 1 .export irq_init
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000000r 1
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000000r 1 .code
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000000r 1
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000000r 1 irq_init:
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000000r 1 60 rts
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000001r 1
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000001r 1 nmi_handler:
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000001r 1 40 rti
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000002r 1
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000002r 1 40 irq_handler: rti
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000003r 1
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000003r 1
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