verilog-apple-one/apple1_syn.prd

#--  Synopsys, Inc.
#--  Version L-2016.09L+ice40
#--  Project file C:\Users\Alan\Desktop\projects\apple1\apple1_syn.prd
#--  Written on Thu Jan 04 21:48:56 2018

#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear
Initial commit 2018-01-02 00:33:20 +11:00			`#-- Synopsys, Inc.`
			`#-- Version L-2016.09L+ice40`
			`#-- Project file C:\Users\Alan\Desktop\projects\apple1\apple1_syn.prd`
Added basic ROM and fiddled things Clock now runs at 6MHz while I try to simplify things to figure out a CPU bug 2018-01-10 16:39:18 +11:00			`#-- Written on Thu Jan 04 21:48:56 2018`
Initial commit 2018-01-02 00:33:20 +11:00
			`#`
			`### Watch Implementation type ###`
			`#`
			`watch_impl -all`
			`#`
			`### Watch Implementation properties ###`
			`#`
			`watch_prop -clear`