Apple-1-HW/verilog-apple-one
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Enabled uart and increased memory to 16kb

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This commit is contained in:
lawrie 2020-04-05 11:03:58 +01:00
parent f3e3659b13
commit 0f9b231dbd
5 changed files with 41 additions and 9 deletions
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30
boards/ulx3s/yosys/slow.py Executable file
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@ -0,0 +1,30 @@
#!/usr/bin/env python3
import time
import os
import sys
if len(sys.argv) != 2:
print("Usage: " + sys.argv[0] + " <filename>")
sys.exit(1)
os.system('stty -F /dev/ttyUSB0 raw -echo 115200')
fin = open(sys.argv[1], "r")
fout = open("/dev/ttyUSB0", "w")
for line in fin:
for ch in line.strip('\n'):
fout.write(ch)
fout.flush()
time.sleep(.1)
fout.write('\r')
fout.flush()
time.sleep(.5)
fin.close()
fout.close()

4
boards/ulx3s/yosys/ulx3s_v20.lpf
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@ -60,11 +60,11 @@ IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
## DIP switch "blinkey", "gpio" sheet
LOCATE COMP "uart_cts" SITE "E8"; # SW1
LOCATE COMP "sw[0]" SITE "E8"; # SW1
LOCATE COMP "sw[1]" SITE "D8"; # SW2
LOCATE COMP "sw[2]" SITE "D7"; # SW3
LOCATE COMP "sw[3]" SITE "E7"; # SW4
IOBUF PORT "uart_cts" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;

4
rtl/apple1.v
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@ -103,7 +103,7 @@ module apple1 #(
//////////////////////////////////////////////////////////////////////////
// Address Decoding
wire ram_cs = (ab[15:13] == 3'b000); // 0x0000 -> 0x1FFF
wire ram_cs = (ab[15:14] == 2'b00); // 0x0000 -> 0x3FFF
// font mode, background and foreground colour
wire vga_mode_cs = (ab[15:2] == 14'b11000000000000); // 0xC000 -> 0xC003
@ -134,7 +134,7 @@ module apple1 #(
.RAM_FILENAME (RAM_FILENAME)
) my_ram(
.clk(clk25),
.address(ab[12:0]),
.address(ab[13:0]),
.w_en(we & ram_cs),
.din(dbo),
.dout(ram_dout)

8
rtl/boards/ulx3s/apple1_dvi.v
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@ -33,7 +33,7 @@ module apple1_top #(
// I/O interface to computer
input uart_rx, // asynchronous serial data input from computer
output uart_tx, // asynchronous serial data output to computer
output uart_cts, // clear to send flag to computer - not used
//output uart_cts, // clear to send flag to computer - not used
// I/O interface to keyboard
input ps2_clk, // PS/2 keyboard serial clock input
@ -46,8 +46,10 @@ module apple1_top #(
// Debugging ports
output [3:0] led,
input [1:0] button // 2 buttons on board
input [1:0] button, // 2 buttons on board
input [3:0] sw
);
wire uart_cts;
parameter C_ddr = 1'b1; // 0:SDR 1:DDR
@ -127,7 +129,7 @@ module apple1_top #(
.ps2_clk(ps2_clk),
.ps2_din(ps2_din),
.ps2_select(1'b1), // PS/2 enabled, UART TX disabled
.ps2_select(sw[0]), // PS/2 enabled, UART TX disabled
//.ps2_select(1'b0), // PS/2 disabled, UART TX enabled
.vga_h_sync(vga_h_sync),

4
rtl/ram.v
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@ -26,13 +26,13 @@ module ram #(
parameter RAM_FILENAME = "../../../roms/ram.hex"
) (
input clk, // clock signal
input [12:0] address, // address bus
input [13:0] address, // address bus
input w_en, // active high write enable strobe
input [7:0] din, // 8-bit data bus (input)
output reg [7:0] dout // 8-bit data bus (output)
);
reg [7:0] ram_data[0:8191];
reg [7:0] ram_data[0:16383];
initial
$readmemh(RAM_FILENAME, ram_data, 0, 8191);