Fixed differences for iceube2 and yosys

boards/ice40hx8k/appleone_sbt.project

@@ -4,7 +4,7 @@ Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Bui
 ProjectName=appleone
 Vendor=SiliconBlue
 Synthesis=synplify
-ProjectVFiles=../../rtl/rom_wozmon.v=work,../../rtl/apple1.v=work,../../rtl/ram.v=work,../../rtl/boards/ice40hx8k/clock_pll.v=work,../../rtl/uart/async_tx_rx.v=work,../../rtl/uart/uart.v=work,../../rtl/boards/ice40hx8k/apple1_hx8k.v=work,../../rtl/cpu/arlet_6502.v=work,../../rtl/cpu/arlet/ALU.v=work,../../rtl/cpu/arlet/cpu.v=work,../../rtl/rom_basic.v
+ProjectVFiles=../../rtl/rom_wozmon.v=work,../../rtl/apple1.v=work,../../rtl/ram.v=work,../../rtl/boards/ice40hx8k/clock_pll.v=work,../../rtl/uart/async_tx_rx.v=work,../../rtl/uart/uart.v=work,../../rtl/boards/ice40hx8k/apple1_hx8k.v=work,../../rtl/cpu/arlet_6502.v=work,../../rtl/cpu/arlet/ALU.v=work,../../rtl/cpu/arlet/cpu.v=work,../../rtl/rom_basic.v=work,../../rtl/pwr_reset.v=work,../../rtl/clock.v=work,../../rtl/ps2keyboard/ps2keyboard.v=work
 ProjectCFiles=appleone_syn.sdc
 CurImplementation=appleone_Implmnt
 Implementations=appleone_Implmnt

boards/ice40hx8k/appleone_syn.prd

@@ -1,7 +1,7 @@
 #--  Synopsys, Inc.
 #--  Version L-2016.09L+ice40
 #--  Project file C:\Users\Alan\Documents\GitHub\apple-one\boards\ice40hx8k\appleone_syn.prd
-#--  Written on Sun Jan 28 00:17:28 2018
+#--  Written on Mon Jan 29 21:24:55 2018
 
 #
 ### Watch Implementation type ###

boards/ice40hx8k/appleone_syn.prj

@@ -19,6 +19,9 @@ add_file -verilog -lib work "../../rtl/cpu/arlet_6502.v"
 add_file -verilog -lib work "../../rtl/cpu/arlet/ALU.v" 
 add_file -verilog -lib work "../../rtl/cpu/arlet/cpu.v" 
 add_file -verilog -lib work "../../rtl/rom_basic.v" 
+add_file -verilog -lib work "../../rtl/pwr_reset.v" 
+add_file -verilog -lib work "../../rtl/clock.v" 
+add_file -verilog -lib work "../../rtl/ps2keyboard/ps2keyboard.v" 
 add_file -constraint -lib work "appleone_syn.sdc"
 #implementation: "appleone_Implmnt"
 impl -add appleone_Implmnt -type fpga

rtl/pwr_reset.v

@@ -5,7 +5,6 @@ module pwr_reset(
     output rst
     );
 
-    wire rst;
     reg hard_reset;
     reg [5:0] reset_cnt;
     wire pwr_up_flag = &reset_cnt;

rtl/ram.v

@@ -6,10 +6,10 @@ module ram(
     output reg [7:0] dout
     );
 
-    `ifdef YOSYS
+    `ifdef SIM
-    parameter RAM_FILENAME = "../../roms/ram.hex";
-    `else
     parameter RAM_FILENAME = "../roms/ram.hex";
+    `else
+    parameter RAM_FILENAME = "../../roms/ram.hex";
     `endif
 
     reg [7:0] ram_data[0:8191];

rtl/rom_basic.v

@@ -4,10 +4,10 @@ module rom_basic(
     output reg [7:0] dout
     );
 
-    `ifdef YOSYS
+    `ifdef SIM
-    parameter BASIC_FILENAME = "../../roms/basic.hex";
-    `else
     parameter BASIC_FILENAME = "../roms/basic.hex";
+    `else
+    parameter BASIC_FILENAME = "../../roms/basic.hex";
     `endif
 
     reg [7:0] rom_data[0:4095];

rtl/rom_wozmon.v

@@ -4,10 +4,10 @@ module rom_wozmon(
     output reg [7:0] dout
     );
 
-    `ifdef YOSYS
+    `ifdef SIM
-    parameter ROM_FILENAME = "../../roms/wozmon.hex";
-    `else
     parameter ROM_FILENAME = "../roms/wozmon.hex";
+    `else
+    parameter ROM_FILENAME = "../../roms/wozmon.hex";
     `endif
 
     reg [7:0] rom_data[0:255];