diff --git a/boards/ice40hx8k/appleone/appleone_sbt.project b/boards/ice40hx8k/appleone_sbt.project similarity index 82% rename from boards/ice40hx8k/appleone/appleone_sbt.project rename to boards/ice40hx8k/appleone_sbt.project index 3c5947b..36b9b8a 100644 --- a/boards/ice40hx8k/appleone/appleone_sbt.project +++ b/boards/ice40hx8k/appleone_sbt.project @@ -4,7 +4,7 @@ Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Bui ProjectName=appleone Vendor=SiliconBlue Synthesis=synplify -ProjectVFiles=../../../rtl/apple1_top.v=work,../../../rtl/boards/ice40hx8k/clocks.v=work,../../../rtl/boards/ice40hx8k/clock_pll.v=work,../../../rtl/cpu/ALU.v=work,../../../rtl/cpu/cpu.v=work,../../../rtl/rom_wozmon.v,../../../rtl/uart/uart.v,../../../rtl/ram.v +ProjectVFiles=../../rtl/rom_wozmon.v,../../rtl/apple1.v,../../rtl/ram.v,../../rtl/boards/ice40hx8k/apple1_top.v,../../rtl/boards/ice40hx8k/clock_pll.v,../../rtl/cpu/ALU.v,../../rtl/cpu/cpu.v,../../rtl/uart/async_tx_rx.v,../../rtl/uart/uart.v ProjectCFiles=appleone_syn.sdc CurImplementation=appleone_Implmnt Implementations=appleone_Implmnt @@ -19,13 +19,13 @@ DevicePower= NetlistFile=appleone_Implmnt/appleone.edf AdditionalEDIFFile= IPEDIFFile= -DesignLib=appleone_Implmnt/sbt/netlist/oadb-top -DesignView=_rt -DesignCell=top +DesignLib= +DesignView= +DesignCell= SynthesisSDCFile=appleone_Implmnt/appleone.scf UserPinConstraintFile= UserSDCFile= -PhysicalConstraintFile=../../../ice40hx8k.pcf +PhysicalConstraintFile= BackendImplPathName= Devicevoltage=1.14 DevicevoltagePerformance=+/-5%(datasheet default) @@ -84,5 +84,5 @@ BitmapSetSecurity=no BitmapSetNoUsedIONoPullup=no FloorPlannerShowFanInNets=yes FloorPlannerShowFanOutNets=yes -HookTo3rdPartyTextEditor= +HookTo3rdPartyTextEditor=no diff --git a/boards/ice40hx8k/appleone/appleone_syn.prj b/boards/ice40hx8k/appleone_syn.prj similarity index 71% rename from boards/ice40hx8k/appleone/appleone_syn.prj rename to boards/ice40hx8k/appleone_syn.prj index d8f2d71..5c604a4 100644 --- a/boards/ice40hx8k/appleone/appleone_syn.prj +++ b/boards/ice40hx8k/appleone_syn.prj @@ -1,15 +1,16 @@ #-- Synopsys, Inc. -#-- Project file C:\Users\Alan\Documents\GitHub\apple-one\boards\ice40hx8k\appleone\appleone_syn.prj +#-- Project file C:\Users\Alan\Documents\GitHub\apple-one\boards\ice40hx8k\appleone_syn.prj #project files -add_file -verilog -lib work "../../../rtl/apple1_top.v" -add_file -verilog -lib work "../../../rtl/boards/ice40hx8k/clocks.v" -add_file -verilog -lib work "../../../rtl/boards/ice40hx8k/clock_pll.v" -add_file -verilog -lib work "../../../rtl/cpu/ALU.v" -add_file -verilog -lib work "../../../rtl/cpu/cpu.v" -add_file -verilog -lib work "../../../rtl/rom_wozmon.v" -add_file -verilog -lib work "../../../rtl/uart/uart.v" -add_file -verilog -lib work "../../../rtl/ram.v" +add_file -verilog -lib work "../../rtl/rom_wozmon.v" +add_file -verilog -lib work "../../rtl/apple1.v" +add_file -verilog -lib work "../../rtl/ram.v" +add_file -verilog -lib work "../../rtl/boards/ice40hx8k/apple1_top.v" +add_file -verilog -lib work "../../rtl/boards/ice40hx8k/clock_pll.v" +add_file -verilog -lib work "../../rtl/cpu/ALU.v" +add_file -verilog -lib work "../../rtl/cpu/cpu.v" +add_file -verilog -lib work "../../rtl/uart/async_tx_rx.v" +add_file -verilog -lib work "../../rtl/uart/uart.v" add_file -constraint -lib work "appleone_syn.sdc" #implementation: "appleone_Implmnt" impl -add appleone_Implmnt -type fpga diff --git a/rtl/apple1_top.v b/rtl/apple1.v similarity index 57% rename from rtl/apple1_top.v rename to rtl/apple1.v index 658908f..982e983 100644 --- a/rtl/apple1_top.v +++ b/rtl/apple1.v @@ -1,22 +1,10 @@ -// -// FIXME: -// there defines must be enabled in the project -// settings to avoid conflicts with different -// development platforms -// -//`define ICE40 -// - -module top( +module apple1( input clk25, // 25 MHz master clock input rst_n, // active low synchronous reset (needed for simulation) input uart_rx, output uart_tx, - output uart_cts, - - output [7:0] led, // what do these do? - output [7:0] ledx // what do these do? + output uart_cts ); ////////////////////////////////////////////////////////////////////////// // Registers and Wires @@ -28,23 +16,6 @@ module top( ////////////////////////////////////////////////////////////////////////// // Clocks - reg cpu_clken; - - // FIXME: - // the clocks here should come from higher up - // the hierarchy, i.e. generated at the board - // level. - // - // if cpu_clken is a simple block, - // keep it here but make it generic. - - `ifdef ICE40 - clocks my_clocks( - .clk(clk), - .clk25(clk25), - .cpu_clken(cpu_clken) - ); - `endif // generate clock enable once every // 25 clocks. This will (hopefully) make @@ -56,6 +27,7 @@ module top( // reg [4:0] clk_div; + reg cpu_clken; always @(posedge clk25) begin // note: clk_div should be compared to @@ -107,8 +79,8 @@ module top( .DI (dbi_c), .DO (dbo_c), .WE (we_c), - .IRQ (1'b0), - .NMI (1'b0), + .IRQ (1'b1), + .NMI (1'b1), .RDY (cpu_clken) ); @@ -162,8 +134,7 @@ module top( .address(ab[1:0]), .w_en(we & uart_cs), .din(dbo), - .dout(uart_dout), - .led(led) + .dout(uart_dout) ); // link up chip selected device to cpu input @@ -171,60 +142,4 @@ module top( rom_cs ? rom_dout : uart_cs ? uart_dout : 8'hFF; - - assign ledx = ab[7:0]; - -// always @(posedge clk25) -// begin -// if (cpu_clken) -// begin -// led <= ab[7:0]; -// ledx <= ~ab[15:8]; -// end -// end - -// reg [7:0] ram[0:8191] /* synthesis syn_ramstyle = "block_ram" */; -// reg [7:0] rom[0:255] /* synthesis syn_ramstyle = "block_ram" */; -// reg [7:0] basic[0:4095] /* synthesis syn_ramstyle = "block_ram" */; -// -// initial begin -// $readmemh("../roms/ram.hex", ram, 0, 8191); -// $readmemh("../roms/rom.hex", rom, 0, 255); -// $readmemh("../roms/basic.hex", basic, 0, 4095); -// end -// -// always @(posedge clk_25) -// begin -// if (phi_clk_en) -// begin -// if (res) -// begin -// case(ab) -// default: -// begin -// if (ab[15:12] == 4'b0000 || ab[15:12] == 4'b0001) -// begin -// // 0x0000 -> 0x1FFF - RAM -// dbi <= ram[ab[12:0]]; -// if (~rw) ram[ab[12:0]] <= dbo; -// end -// else if (ab[15:12] == 4'b1110) -// begin -// // 0xE000 -> 0xEFFF - BASIC -// dbi <= basic[ab[11:0]]; -// end -// else if (ab[15:8] == 8'b11111111) -// begin -// // 0xFF00 -> 0xFFFF - ROM -// dbi <= rom[ab[7:0]]; -// end -// else -// // unknown address return zero -// dbi <= 8'h0; -// end -// -// endcase -// end -// end -// end endmodule diff --git a/rtl/boards/ice40hx8k/apple1_top.v b/rtl/boards/ice40hx8k/apple1_top.v new file mode 100644 index 0000000..075fdab --- /dev/null +++ b/rtl/boards/ice40hx8k/apple1_top.v @@ -0,0 +1,28 @@ +module apple1_top( + input clk, // 12 MHz board clock + + input uart_rx, + output uart_tx, + output uart_cts +); + + wire clk25; + + // 12MHz up to 25MHz + clock_pll clock_pll_inst( + .REFERENCECLK(clk), + .PLLOUTCORE(), + .PLLOUTGLOBAL(clk25), + .RESET(1'b1) + ); + + // apple one main system + apple1 my_apple1( + .clk25(clk25), + .rst_n(1'b1), + .uart_rx(uart_rx), + .uart_tx(uart_tx), + .uart_cts(uart_cts) + ); + +endmodule diff --git a/rtl/boards/ice40hx8k/clocks.v b/rtl/boards/ice40hx8k/clocks.v deleted file mode 100644 index f9c5881..0000000 --- a/rtl/boards/ice40hx8k/clocks.v +++ /dev/null @@ -1,34 +0,0 @@ -module clocks ( - input clk, - output clk25, - - output reg cpu_clken -); - - // 12MHz up to 25MHz - clock_pll clock_pll_inst( - .REFERENCECLK(clk), - .PLLOUTCORE(), - .PLLOUTGLOBAL(clk25), - .RESET(1'b1) - ); - - reg [25:0] clk_div; - - always @(posedge clk25) - begin - if (clk_div == 12000000) - clk_div <= 0; - else - clk_div <= clk_div + 1; - - // 1MHz - cpu_clken <= (clk_div[25:0] == 0); - - // 2MHz - //cpu_clken <= (clk_div[4] == 0) & (clk_div[2:0] == 0); - - // 4MHz - //cpu_clken <= (clk_div[4] == 0) & (clk_div[1:0] == 0); - end -endmodule diff --git a/rtl/uart/uart.v b/rtl/uart/uart.v index 2046c4e..1c0aa88 100644 --- a/rtl/uart/uart.v +++ b/rtl/uart/uart.v @@ -15,8 +15,7 @@ module uart( input uart_rx, output uart_tx, - output uart_cts, - output reg [7:0] led + output uart_cts ); parameter ClkFrequency = 25000000; // 25MHz @@ -76,8 +75,6 @@ module uart( uart_tx_stb <= 0; uart_rx_ack <= 0; - led[7] <= uart_rx_status; - if (enable) begin case (address) @@ -113,7 +110,6 @@ module uart( begin dout <= {uart_rx_status, uart_rx_byte[6:0]}; uart_rx_ack <= 1'b1; - led[6:0] <= uart_rx_byte[6:0]; end end endcase