Apple-1-HW/verilog-apple-one
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Updated DE0 project to have 0xC00X colour support.

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This commit is contained in:
Niels Moseley 2018-05-09 02:59:11 +02:00
parent e475262a2a
commit 157af7c111
5 changed files with 25 additions and 16 deletions
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16
boards/spartan3e_starterkit/webpack_ise/Apple-One.gise
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@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1518997497" xil_pn:in_ck="-2402892782883100176" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8720043281624233679" xil_pn:start_ts="1518997476">
<transform xil_pn:end_ts="1518998485" xil_pn:in_ck="-2402892782883100176" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8720043281624233679" xil_pn:start_ts="1518998464">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -121,11 +121,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1518445424" xil_pn:in_ck="-5976217886481463465" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-5004538815383072947" xil_pn:start_ts="1518445424">
<transform xil_pn:end_ts="1518998485" xil_pn:in_ck="-5976217886481463465" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-5004538815383072947" xil_pn:start_ts="1518998485">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1518997502" xil_pn:in_ck="-3894786652928293112" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-581701490373080307" xil_pn:start_ts="1518997497">
<transform xil_pn:end_ts="1518998490" xil_pn:in_ck="-3894786652928293112" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-581701490373080307" xil_pn:start_ts="1518998485">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@ -134,9 +134,11 @@
<outfile xil_pn:name="apple1_s3e_starterkit_top.ngd"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1518997506" xil_pn:in_ck="8375880660293788329" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1518997502">
<transform xil_pn:end_ts="1518998495" xil_pn:in_ck="8375880660293788329" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1518998490">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top.pcf"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top_map.map"/>
@ -147,7 +149,7 @@
<outfile xil_pn:name="apple1_s3e_starterkit_top_summary.xml"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1518997523" xil_pn:in_ck="-3296291810439397278" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1518997506">
<transform xil_pn:end_ts="1518998512" xil_pn:in_ck="-3296291810439397278" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1518998495">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -161,7 +163,7 @@
<outfile xil_pn:name="apple1_s3e_starterkit_top_pad.txt"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1518997534" xil_pn:in_ck="-5976217886481471090" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1518997523">
<transform xil_pn:end_ts="1518998523" xil_pn:in_ck="-5976217886481471090" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1518998512">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@ -185,7 +187,7 @@
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1518997523" xil_pn:in_ck="-6485470272289971291" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518997520">
<transform xil_pn:end_ts="1518998512" xil_pn:in_ck="-6485470272289971291" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518998508">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

BIN
boards/spartan3e_starterkit/webpack_ise/apple1_s3e_starterkit_top.ipf
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3
boards/spartan3e_starterkit/webpack_ise/apple1_s3e_starterkit_top.ucf
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@ -24,6 +24,9 @@ NET "UART_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
# RESET BUTTON / SOUTH on the board
NET "BUTTON" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
# INPUT SELECTION SWITCH (PS/2 vs. UART)
NET "SWITCH" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
#Created by Constraints Editor (xc3s500e-fg320-4) - 2018/02/11
NET "CLK_50MHZ" TNM_NET = CLK_50MHZ;
NET "clk25" TNM_NET = clk25;

5
rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v
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@ -39,7 +39,8 @@ module apple1_s3e_starterkit_top #(
input PS2_KBCLK,
input PS2_KBDAT,
input BUTTON,
input BUTTON, // Button for RESET
input SWITCH, // Switch between PS/2 input and UART
output VGA_R,
output VGA_G,
@ -78,7 +79,7 @@ module apple1_s3e_starterkit_top #(
//.uart_cts(UART_CTS), // there is no CTS on the board :(
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.ps2_select(1'b1),
.ps2_select(SWITCH),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(VGA_R),

17
rtl/boards/terasic_de0/apple1_de0_top.v
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@ -64,7 +64,7 @@ module apple1_de0_top #(
clk25 <= ~clk25;
end
wire vga_bit;
wire r_bit, g_bits, b_bits;
//////////////////////////////////////////////////////////////////////////
// Core of system
@ -85,16 +85,19 @@ module apple1_de0_top #(
.ps2_select(1'b1),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(vga_bit),
//.vga_grn(vga_bit),
//.vga_blu(vga_bit),
.vga_red(r_bit),
.vga_grn(g_bit),
.vga_blu(b_bit),
.pc_monitor(pc_monitor)
);
// set the monochrome base colour here..
assign VGA_R[3:0] = vga_bit ? 4'b1000 : 4'b0000;
assign VGA_G[3:0] = vga_bit ? 4'b1111 : 4'b0000;
assign VGA_B[3:0] = vga_bit ? 4'b1000 : 4'b0000;
assign VGA_R[3] = r_bit;
assign VGA_G[3] = g_bit;
assign VGA_B[3] = b_bit;
assign VGA_R[2:0] = 3'b000;
assign VGA_G[2:0] = 3'b000;
assign VGA_B[2:0] = 3'b000;
//////////////////////////////////////////////////////////////////////////
// Display 6502 address on 7-segment displays