wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok
This commit is contained in:
Alan Garfield
parent
2432225d01
commit
20919fa726
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@ -33,157 +33,11 @@ module apple1_tb;
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initial begin
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// force core_top.clk_div = 0;
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// force core_top.cpu_clken = 0;
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// force core_top.hard_reset = 0;
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// force core_top.reset_cnt = 0;
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// force core_top.my_cpu.arlet_cpu.AB = 0;
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// force core_top.my_cpu.arlet_cpu.PC = 0;
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// force core_top.my_cpu.arlet_cpu.ABL = 0;
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// force core_top.my_cpu.arlet_cpu.ABH = 0;
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// force core_top.my_cpu.arlet_cpu.DIHOLD = 0;
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// force core_top.my_cpu.arlet_cpu.IRHOLD = 0;
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// force core_top.my_cpu.arlet_cpu.IRHOLD_valid = 0;
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// force core_top.my_cpu.arlet_cpu.C = 0;
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// force core_top.my_cpu.arlet_cpu.Z = 0;
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// force core_top.my_cpu.arlet_cpu.I = 0;
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// force core_top.my_cpu.arlet_cpu.D = 0;
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// force core_top.my_cpu.arlet_cpu.V = 0;
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// force core_top.my_cpu.arlet_cpu.N = 0;
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// force core_top.my_cpu.arlet_cpu.AI = 0;
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// force core_top.my_cpu.arlet_cpu.BI = 0;
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// force core_top.my_cpu.arlet_cpu.DO = 0;
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// force core_top.my_cpu.arlet_cpu.WE = 0;
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// force core_top.my_cpu.arlet_cpu.CI = 0;
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// force core_top.my_cpu.arlet_cpu.NMI_edge = 0;
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// force core_top.my_cpu.arlet_cpu.regsel = 0;
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// force core_top.my_cpu.arlet_cpu.PC_inc = 0;
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// force core_top.my_cpu.arlet_cpu.PC_temp = 0;
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// force core_top.my_cpu.arlet_cpu.src_reg = 0;
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// force core_top.my_cpu.arlet_cpu.dst_reg = 0;
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// force core_top.my_cpu.arlet_cpu.index_y = 0;
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// force core_top.my_cpu.arlet_cpu.load_reg = 0;
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// force core_top.my_cpu.arlet_cpu.inc = 0;
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// force core_top.my_cpu.arlet_cpu.write_back = 0;
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// force core_top.my_cpu.arlet_cpu.load_only = 0;
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// force core_top.my_cpu.arlet_cpu.store = 0;
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// force core_top.my_cpu.arlet_cpu.adc_sbc = 0;
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// force core_top.my_cpu.arlet_cpu.compare = 0;
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// force core_top.my_cpu.arlet_cpu.shift = 0;
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// force core_top.my_cpu.arlet_cpu.rotate = 0;
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// force core_top.my_cpu.arlet_cpu.backwards = 0;
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// force core_top.my_cpu.arlet_cpu.cond_true = 0;
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// force core_top.my_cpu.arlet_cpu.cond_code = 0;
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// force core_top.my_cpu.arlet_cpu.shift_right = 0;
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// force core_top.my_cpu.arlet_cpu.alu_shift_right = 0;
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// force core_top.my_cpu.arlet_cpu.op = 0;
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// force core_top.my_cpu.arlet_cpu.alu_op = 0;
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// force core_top.my_cpu.arlet_cpu.adc_bcd = 0;
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// force core_top.my_cpu.arlet_cpu.adj_bcd = 0;
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// force core_top.my_cpu.arlet_cpu.bit_ins = 0;
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// force core_top.my_cpu.arlet_cpu.plp = 0;
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// force core_top.my_cpu.arlet_cpu.php = 0;
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// force core_top.my_cpu.arlet_cpu.clc = 0;
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// force core_top.my_cpu.arlet_cpu.sed = 0;
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// force core_top.my_cpu.arlet_cpu.cli = 0;
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// force core_top.my_cpu.arlet_cpu.sei = 0;
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// force core_top.my_cpu.arlet_cpu.clv = 0;
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// force core_top.my_cpu.arlet_cpu.brk = 0;
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// force core_top.my_cpu.arlet_cpu.res = 0;
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// force core_top.my_cpu.arlet_cpu.write_register = 0;
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// force core_top.my_cpu.arlet_cpu.ADJL = 0;
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// force core_top.my_cpu.arlet_cpu.ADJH = 0;
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// force core_top.my_cpu.arlet_cpu.NMI_1 = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.OUT = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.CO = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.N = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.HC = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.AI7 = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.BI7 = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.temp_logic = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.temp_BI = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.temp_l = 0;
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// force core_top.my_cpu.arlet_cpu.ALU.temp_h = 0;
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clk25 = 1'b0;
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uart_rx = 1'b1;
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rst_n = 1'b0;
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#40 rst_n = 1'b1;
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// release core_top.clk_div;
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// release core_top.cpu_clken;
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// release core_top.hard_reset;
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// release core_top.reset_cnt;
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// release core_top.my_cpu.arlet_cpu.AB;
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// release core_top.my_cpu.arlet_cpu.PC;
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// release core_top.my_cpu.arlet_cpu.ABL;
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// release core_top.my_cpu.arlet_cpu.ABH;
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// release core_top.my_cpu.arlet_cpu.DIHOLD;
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// release core_top.my_cpu.arlet_cpu.IRHOLD;
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// release core_top.my_cpu.arlet_cpu.IRHOLD_valid;
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// release core_top.my_cpu.arlet_cpu.C;
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// release core_top.my_cpu.arlet_cpu.Z;
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// release core_top.my_cpu.arlet_cpu.I;
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// release core_top.my_cpu.arlet_cpu.D;
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// release core_top.my_cpu.arlet_cpu.V;
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// release core_top.my_cpu.arlet_cpu.N;
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// release core_top.my_cpu.arlet_cpu.AI;
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// release core_top.my_cpu.arlet_cpu.BI;
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// release core_top.my_cpu.arlet_cpu.DO;
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// release core_top.my_cpu.arlet_cpu.WE;
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// release core_top.my_cpu.arlet_cpu.CI;
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// release core_top.my_cpu.arlet_cpu.NMI_edge;
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// release core_top.my_cpu.arlet_cpu.regsel;
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// release core_top.my_cpu.arlet_cpu.PC_inc;
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// release core_top.my_cpu.arlet_cpu.PC_temp;
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// release core_top.my_cpu.arlet_cpu.src_reg;
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// release core_top.my_cpu.arlet_cpu.dst_reg;
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// release core_top.my_cpu.arlet_cpu.index_y;
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// release core_top.my_cpu.arlet_cpu.load_reg;
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// release core_top.my_cpu.arlet_cpu.inc;
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// release core_top.my_cpu.arlet_cpu.write_back;
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// release core_top.my_cpu.arlet_cpu.load_only;
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// release core_top.my_cpu.arlet_cpu.store;
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// release core_top.my_cpu.arlet_cpu.adc_sbc;
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// release core_top.my_cpu.arlet_cpu.compare;
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// release core_top.my_cpu.arlet_cpu.shift;
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// release core_top.my_cpu.arlet_cpu.rotate;
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// release core_top.my_cpu.arlet_cpu.backwards;
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// release core_top.my_cpu.arlet_cpu.cond_true;
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// release core_top.my_cpu.arlet_cpu.cond_code;
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// release core_top.my_cpu.arlet_cpu.shift_right;
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// release core_top.my_cpu.arlet_cpu.alu_shift_right;
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// release core_top.my_cpu.arlet_cpu.op;
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// release core_top.my_cpu.arlet_cpu.alu_op;
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// release core_top.my_cpu.arlet_cpu.adc_bcd;
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// release core_top.my_cpu.arlet_cpu.adj_bcd;
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// release core_top.my_cpu.arlet_cpu.bit_ins;
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// release core_top.my_cpu.arlet_cpu.plp;
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// release core_top.my_cpu.arlet_cpu.php;
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// release core_top.my_cpu.arlet_cpu.clc;
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// release core_top.my_cpu.arlet_cpu.sec;
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// release core_top.my_cpu.arlet_cpu.cld;
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// release core_top.my_cpu.arlet_cpu.sed;
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// release core_top.my_cpu.arlet_cpu.sei;
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// release core_top.my_cpu.arlet_cpu.clv;
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// release core_top.my_cpu.arlet_cpu.brk;
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// release core_top.my_cpu.arlet_cpu.res;
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// release core_top.my_cpu.arlet_cpu.write_register;
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// release core_top.my_cpu.arlet_cpu.ADJL;
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// release core_top.my_cpu.arlet_cpu.ADJH;
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// release core_top.my_cpu.arlet_cpu.NMI_1;
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// release core_top.my_cpu.arlet_cpu.ALU.OUT;
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// release core_top.my_cpu.arlet_cpu.ALU.CO;
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// release core_top.my_cpu.arlet_cpu.ALU.N;
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// release core_top.my_cpu.arlet_cpu.ALU.HC;
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// release core_top.my_cpu.arlet_cpu.ALU.AI7;
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// release core_top.my_cpu.arlet_cpu.ALU.BI7;
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// release core_top.my_cpu.arlet_cpu.ALU.temp_logic;
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// release core_top.my_cpu.arlet_cpu.ALU.temp_BI;
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// release core_top.my_cpu.arlet_cpu.ALU.temp_l;
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// release core_top.my_cpu.arlet_cpu.ALU.temp_h;
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$display("Starting...");
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$dumpfile("apple1_top_tb.vcd");
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$dumpvars;
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@ -0,0 +1,2 @@
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iverilog -DSIM -g2005 -s vga_tb -o vga_tb -c vga_files.txt
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vvp vga_tb
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@ -0,0 +1,4 @@
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../rtl/vga/vga.v
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../rtl/vga/vram.v
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../rtl/vga/font_rom.v
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vga_tb.v
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@ -0,0 +1,95 @@
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level test bench for apple1_top
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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`timescale 1ns/1ps
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module vga_tb;
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reg clk25, rst, address, w_en, blink_clken;
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reg [7:0] din;
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wire vga_h_sync, vga_v_sync, vga_red, vga_grn, vga_blu;
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//////////////////////////////////////////////////////////////////////////
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// Setup dumping of data for inspection
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initial begin
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clk25 = 1'b0;
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rst = 1'b0;
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address = 1'b0;
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w_en = 1'b0;
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blink_clken = 1'b0;
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din = 8'd0;
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#5
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rst = 1'b1;
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#5
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rst = 1'b0;
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$display("Starting...");
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$dumpfile("vga_tb.vcd");
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$dumpvars;
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//#180000
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//uart_rx = 1'b0;
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//#400
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//uart_rx = 1'b1;
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//#400
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//uart_rx = 1'b0;
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//#400
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//uart_rx = 1'b1;
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//#800
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//uart_rx = 1'b0;
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//#1600
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//uart_rx = 1'b1;
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#50000000 $display("Stopping...");
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$finish;
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end
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//////////////////////////////////////////////////////////////////////////
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// Clock
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always
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#20 clk25 = !clk25;
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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vga my_vga (
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.clk25(clk25),
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.enable(1'b1),
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.rst(rst),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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.vga_grn(vga_grn),
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.vga_blu(vga_blu),
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.address(address),
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.w_en(w_en),
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.din(din),
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.blink_clken(blink_clken)
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);
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endmodule
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1088
roms/vga_font.bin
1088
roms/vga_font.bin
File diff suppressed because it is too large
Load Diff
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@ -1,3 +1,67 @@
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000001
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000010
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000011
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000100
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000101
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000110
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000111
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001000
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001001
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001010
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001011
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001100
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001101
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001110
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001111
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010000
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010001
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010010
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010011
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010100
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010101
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010110
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010111
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011000
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011001
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011010
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011011
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011100
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011101
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011110
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011111
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100000
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100001
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100010
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100011
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100100
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100101
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100110
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100111
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101000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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100000
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@ -0,0 +1,54 @@
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: 8KB RAM for system
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//
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// Author.....: Alan Garfield
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// Date.......: 3-2-2018
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//
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module font_rom(
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input clk, // clock signal
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input [5:0] character, // address bus
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input [3:0] pixel, // address of the pixel to output
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input [4:0] line, // address of the line to output
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output reg out // single pixel from address and pixel pos
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);
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`ifdef SIM
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parameter ROM_FILENAME = "../roms/vga_font.bin";
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`else
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parameter ROM_FILENAME = "../../roms/vga_font.bin";
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`endif
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reg [7:0] rom[0:639];
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initial
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$readmemb(ROM_FILENAME, rom, 0, 639);
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// double width of pixel by ignoring bit 0
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wire [2:0] pixel_ptr;
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assign pixel_ptr = (3'h7 - pixel[3:1]);
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// double height of pixel by ignoring bit 0
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wire [3:0] line_ptr = line[4:1];
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always @(posedge clk)
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out <= rom[(character * 10) + {2'd0, line_ptr}][pixel_ptr];
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endmodule
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395
rtl/vga/vga.v
395
rtl/vga/vga.v
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@ -10,300 +10,219 @@ module vga(
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input address, // address bus
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input w_en, // active high write enable strobe
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input [7:0] din, // 8-bit data bas (input)
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input clr_screen_btn, // active high clear screen button
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input blink_clken, // cursor blink enable strobe
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output [15:0] debug
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input blink_clken // cursor blink enable strobe
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);
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reg [4:0] c_rom[0:447] /* synthesis syn_ramstyle = "block_ram" */;
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initial begin
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$readmemb("../../roms/vga_font.bin", c_rom, 0, 447);
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end
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reg [9:0] vram_r_addr;
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reg [9:0] vram_w_addr;
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reg vram_r_en;
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reg vram_w_en;
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reg [5:0] vram_din;
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reg [5:0] vram_dout;
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vram my_vram(
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.clk(clk25),
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.read_addr(vram_r_addr),
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.write_addr(vram_w_addr),
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.r_en(vram_r_en),
|
||||
.w_en(vram_w_en),
|
||||
.din(vram_din),
|
||||
.dout(vram_dout)
|
||||
);
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
// VGA Sync Generation
|
||||
|
||||
// video structure constants
|
||||
parameter hpixels = 800; // horizontal pixels per line
|
||||
parameter vlines = 521; // vertical lines per frame
|
||||
parameter hpulse = 96; // hsync pulse length
|
||||
parameter vpulse = 2; // vsync pulse length
|
||||
parameter h_pixels = 799; // horizontal pixels per line
|
||||
parameter v_lines = 520; // vertical lines per frame
|
||||
parameter h_pulse = 96; // hsync pulse length
|
||||
parameter v_pulse = 2; // vsync pulse length
|
||||
parameter hbp = 144; // end of horizontal back porch
|
||||
parameter hfp = 784; // beginning of horizontal front porch
|
||||
parameter vbp = 31; // end of vertical back porch
|
||||
parameter vfp = 511; // beginning of vertical front porch
|
||||
|
||||
// registers for storing the horizontal & vertical counters
|
||||
reg [9:0] hc;
|
||||
reg [9:0] vc;
|
||||
reg [5:0] hpos;
|
||||
reg [4:0] vpos;
|
||||
reg [3:0] hdot;
|
||||
reg [4:0] vdot;
|
||||
reg [9:0] h_cnt;
|
||||
reg [9:0] v_cnt;
|
||||
wire [3:0] h_dot;
|
||||
reg [4:0] v_dot;
|
||||
|
||||
reg [5:0] h_cursor;
|
||||
reg [4:0] v_cursor;
|
||||
|
||||
wire vga_h_act;
|
||||
wire vga_v_act;
|
||||
wire h_active;
|
||||
wire v_active;
|
||||
assign h_active = (h_cnt >= hbp && h_cnt < hfp);
|
||||
assign v_active = (v_cnt >= vbp && v_cnt < vfp);
|
||||
|
||||
assign vga_h_act = (hc >= hbp && hc < hfp);
|
||||
assign vga_v_act = (vc >= vbp && vc < vfp);
|
||||
|
||||
assign vga_h_sync = (hc < hpulse) ? 0 : 1;
|
||||
assign vga_v_sync = (vc < vpulse) ? 0 : 1;
|
||||
//assign vblank = (vc >= vbp && vc < vfp) ? 0:1;
|
||||
|
||||
always @(posedge clk25)
|
||||
begin
|
||||
if (hc < hpixels - 1)
|
||||
begin
|
||||
hc <= hc + 1;
|
||||
|
||||
// count 16 pixels, so 640px / 16 = 40 characters
|
||||
if (vga_h_act)
|
||||
begin
|
||||
hdot <= hdot + 1;
|
||||
|
||||
if (hdot == 4'hF)
|
||||
begin
|
||||
hdot <= 0;
|
||||
hpos <= hpos + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
// reset horizontal counters
|
||||
hc <= 0;
|
||||
hdot <= 0;
|
||||
hpos <= 0;
|
||||
|
||||
if (vc < vlines - 1)
|
||||
begin
|
||||
vc <= vc + 1;
|
||||
|
||||
// count 20 rows, so 480px / 20 = 24 rows
|
||||
if (vga_v_act)
|
||||
begin
|
||||
vdot <= vdot + 1;
|
||||
|
||||
if (vdot == 5'd19)
|
||||
begin
|
||||
vdot <= 0;
|
||||
vpos <= vpos + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
// reset vertical counters
|
||||
vc <= 0;
|
||||
vdot <= 0;
|
||||
vpos <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg out;
|
||||
assign vga_red = out;
|
||||
assign vga_grn = out;
|
||||
assign vga_blu = out;
|
||||
|
||||
reg [8:0] cur_chr_offset;
|
||||
reg [9:0] v_pos_offset;
|
||||
reg [3:0] v_offset;
|
||||
reg [2:0] h_offset;
|
||||
reg blink;
|
||||
assign vga_h_sync = (h_cnt < h_pulse) ? 0 : 1;
|
||||
assign vga_v_sync = (v_cnt < v_pulse) ? 0 : 1;
|
||||
|
||||
always @(posedge clk25 or posedge rst)
|
||||
begin
|
||||
if (rst)
|
||||
begin
|
||||
vram_r_addr = 10'd0;
|
||||
vram_r_en = 1'b0;
|
||||
h_cnt <= 10'd0;
|
||||
v_cnt <= 10'd0;
|
||||
v_dot <= 5'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// get the current character from vram and build
|
||||
// offset to map into character ROM (5x7 font)
|
||||
if (blink && (hpos == h_cursor && vpos == v_cursor))
|
||||
cur_chr_offset = 9'd0; // the @ character
|
||||
if (h_cnt < h_pixels)
|
||||
h_cnt <= h_cnt + 1;
|
||||
|
||||
else
|
||||
begin
|
||||
vram_r_en = 1'b1;
|
||||
v_pos_offset = (vpos * 40);
|
||||
vram_r_addr = (v_pos_offset + {4'b0, hpos});
|
||||
cur_chr_offset = (vram_dout * 7);
|
||||
// reset horizontal counters
|
||||
h_cnt <= 0;
|
||||
|
||||
//cur_chr_offset <= (v_ram[hpos + (40 * vpos)] * 7);
|
||||
end
|
||||
|
||||
case ({vga_h_act, vga_v_act})
|
||||
default:
|
||||
// outside display area
|
||||
out = 1'b0;
|
||||
|
||||
2'b11:
|
||||
begin
|
||||
// we're inside the visible screen display frame
|
||||
//
|
||||
// scan doubling is achieved by ignoring bit 0 of both vdot
|
||||
// and hdot counters, in affect doubling the pixel size
|
||||
// (each pixel becomes screen pixels)
|
||||
case (vdot[4:1])
|
||||
4'b0000,
|
||||
4'b0001,
|
||||
4'b1001:
|
||||
if (v_cnt < v_lines)
|
||||
begin
|
||||
// blank lines for spacing
|
||||
out = 1'b0;
|
||||
end
|
||||
v_cnt <= v_cnt + 1;
|
||||
|
||||
default:
|
||||
// count 20 rows, so 480px / 20 = 24 rows
|
||||
if (v_active)
|
||||
begin
|
||||
v_dot <= v_dot + 1;
|
||||
|
||||
if (v_dot == 5'd19)
|
||||
v_dot <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
// work out character rom offset for current line
|
||||
// taking away 2 from counter to allow for the two
|
||||
// blank preceding lines
|
||||
v_offset = (vdot[4:1] - 2);
|
||||
|
||||
case (hdot[3:1])
|
||||
3'b000,
|
||||
3'b110,
|
||||
3'b111:
|
||||
begin
|
||||
// blank columns for spacing
|
||||
out = 1'b0;
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
// work out the character rom offset for the current
|
||||
// column. We reverse the dot pattern by subtracting
|
||||
// the column from the number of pixel in the
|
||||
// character row in rom
|
||||
h_offset = (5 - hdot[3:1]);
|
||||
|
||||
// grab the pixel from the character rom for
|
||||
// the given screen column and line
|
||||
out = c_rom[cur_chr_offset + {5'b0, v_offset}][h_offset];
|
||||
end
|
||||
endcase
|
||||
// reset vertical counters
|
||||
v_cnt <= 0;
|
||||
v_dot <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg cls_flag, cls_running;
|
||||
// count 16 pixels, so 640px / 16 = 40 characters
|
||||
assign h_dot = h_active ? h_cnt[3:0] : 4'd0;
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
// Character ROM
|
||||
|
||||
wire [5:0] font_char;
|
||||
wire [3:0] font_pixel;
|
||||
wire [4:0] font_line;
|
||||
wire font_out;
|
||||
|
||||
font_rom my_font_rom(
|
||||
.clk(clk25),
|
||||
.character(font_char),
|
||||
.pixel(font_pixel),
|
||||
.line(font_line),
|
||||
.out(font_out)
|
||||
);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
// Video RAM
|
||||
|
||||
wire [9:0] vram_r_addr;
|
||||
reg [9:0] vram_w_addr;
|
||||
reg vram_w_en;
|
||||
reg [5:0] vram_din;
|
||||
wire [5:0] vram_dout;
|
||||
|
||||
vram my_vram(
|
||||
.clk(clk25),
|
||||
.rst(rst),
|
||||
.read_addr(vram_r_addr),
|
||||
.write_addr(vram_w_addr),
|
||||
.r_en(h_active),
|
||||
.w_en(vram_w_en),
|
||||
.din(vram_din),
|
||||
.dout(vram_dout)
|
||||
);
|
||||
|
||||
|
||||
reg [5:0] vram_h_addr;
|
||||
reg [9:0] vram_v_addr;
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
// Video Signal Generation
|
||||
|
||||
always @(posedge clk25 or posedge rst) begin
|
||||
if (rst) begin
|
||||
vram_h_addr <= 0;
|
||||
vram_v_addr <= 0;
|
||||
end else begin
|
||||
// start the pipeline for reading vram and font details
|
||||
// 3 pixel clock cycles early
|
||||
if (h_dot == 4'hC)
|
||||
vram_h_addr <= vram_h_addr + 1;
|
||||
|
||||
// advance to next row when last display line is reached for row
|
||||
if (v_dot == 5'd19 && h_cnt == 10'd0)
|
||||
vram_v_addr <= vram_v_addr + 10'h28;
|
||||
|
||||
// clear the address registers if we're not in visible area
|
||||
if (~h_active)
|
||||
vram_h_addr <= 0;
|
||||
if (~v_active)
|
||||
vram_v_addr <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign vram_r_addr = ({4'd0, vram_h_addr} + vram_v_addr);
|
||||
assign font_char = vram_dout;
|
||||
assign font_pixel = h_dot + 1; // offset by one to get pixel into right cycle,
|
||||
// font output one pixel clk behind
|
||||
assign font_line = v_dot;
|
||||
|
||||
assign vga_red = font_out;
|
||||
assign vga_grn = font_out;
|
||||
assign vga_blu = font_out;
|
||||
|
||||
reg char_seen;
|
||||
|
||||
always @(posedge clk25 or posedge rst)
|
||||
begin
|
||||
if (rst)
|
||||
begin
|
||||
blink <= 1'b1;
|
||||
h_cursor <= 6'd0;
|
||||
v_cursor <= 5'd0;
|
||||
char_seen <= 0;
|
||||
debug <= 0;
|
||||
cls_running <= 0;
|
||||
cls_flag <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (cls_flag || clr_screen_btn)
|
||||
vram_w_en <= 0;
|
||||
|
||||
if (address == 1'b0) // address low == TX register
|
||||
begin
|
||||
if ((vpos == 0) && (hpos == 0))
|
||||
cls_running <= 1;
|
||||
|
||||
if (cls_running)
|
||||
if (enable & w_en & ~char_seen)
|
||||
begin
|
||||
// clear the vram using the position pointers
|
||||
// very similar to the original apple 1 :)
|
||||
vram_w_addr <= ((vpos * 40) + {4'b0, hpos});
|
||||
vram_din <= 6'd0;
|
||||
vram_w_en <= 1;
|
||||
// incoming character
|
||||
char_seen <= 1;
|
||||
|
||||
if ((vpos == 23) && (hpos == 40))
|
||||
case(din)
|
||||
8'h8D:
|
||||
begin
|
||||
cls_running <= 0;
|
||||
// handle carriage return
|
||||
h_cursor <= 0;
|
||||
v_cursor <= v_cursor + 1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
cls_flag <= 0;
|
||||
end
|
||||
end
|
||||
begin
|
||||
vram_w_en <= 0;
|
||||
|
||||
if (address == 1'b0) // address low == TX register
|
||||
begin
|
||||
if (enable & w_en & ~char_seen)
|
||||
8'h7F:
|
||||
// ignore the DDR call to the PIA
|
||||
h_cursor <= h_cursor + 1;
|
||||
|
||||
default:
|
||||
begin
|
||||
// incoming character
|
||||
debug <= {8'd0, din};
|
||||
char_seen <= 1;
|
||||
|
||||
case(din)
|
||||
8'h8D:
|
||||
begin
|
||||
// handle carriage return
|
||||
h_cursor <= 0;
|
||||
v_cursor <= v_cursor + 1;
|
||||
end
|
||||
|
||||
8'h7F:
|
||||
// ignore the DDR call to the PIA
|
||||
h_cursor <= h_cursor + 1;
|
||||
|
||||
default:
|
||||
begin
|
||||
vram_w_addr <= ((v_cursor * 40) + {4'b0, h_cursor});
|
||||
vram_din <= {~din[6], din[4:0]};
|
||||
vram_w_en <= 1;
|
||||
|
||||
h_cursor <= h_cursor + 1;
|
||||
end
|
||||
endcase
|
||||
|
||||
if (h_cursor == 39)
|
||||
begin
|
||||
h_cursor <= 0;
|
||||
v_cursor <= v_cursor + 1;
|
||||
end
|
||||
|
||||
if (v_cursor == 23)
|
||||
begin
|
||||
// here we need to add the scroll, probably by moving the
|
||||
// HEAD of vram up one line
|
||||
v_cursor <= 0;
|
||||
end
|
||||
vram_w_addr <= ((v_cursor * 40) + {4'b0, h_cursor});
|
||||
vram_din <= {~din[6], din[4:0]};
|
||||
vram_w_en <= 1;
|
||||
|
||||
h_cursor <= h_cursor + 1;
|
||||
end
|
||||
else if(~enable & ~w_en)
|
||||
char_seen <= 0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
if (blink_clken)
|
||||
blink <= ~blink;
|
||||
if (h_cursor == 39)
|
||||
begin
|
||||
h_cursor <= 0;
|
||||
v_cursor <= v_cursor + 1;
|
||||
end
|
||||
|
||||
if (v_cursor == 23)
|
||||
begin
|
||||
// here we need to add the scroll, probably by moving the
|
||||
// HEAD of vram up one line
|
||||
v_cursor <= 0;
|
||||
end
|
||||
|
||||
end
|
||||
else if(~enable & ~w_en)
|
||||
char_seen <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
|
||||
module vram(
|
||||
input clk, // clock signal
|
||||
input rst, //
|
||||
input [9:0] read_addr, // read address bus
|
||||
input [9:0] write_addr, // write address bus
|
||||
input r_en, // active high read enable strobe
|
||||
|
|
@ -33,7 +34,7 @@ module vram(
|
|||
);
|
||||
|
||||
`ifdef SIM
|
||||
parameter RAM_FILENAME = "../roms/ram.hex";
|
||||
parameter RAM_FILENAME = "../roms/vga_vram.bin";
|
||||
`else
|
||||
parameter RAM_FILENAME = "../../roms/vga_vram.bin";
|
||||
`endif
|
||||
|
|
@ -41,13 +42,19 @@ module vram(
|
|||
reg [5:0] ram_data[0:1023];
|
||||
|
||||
initial
|
||||
$readmemb(RAM_FILENAME, ram_data, 0, 1024);
|
||||
$readmemb(RAM_FILENAME, ram_data, 0, 1023);
|
||||
|
||||
always @(posedge clk)
|
||||
always @(posedge clk or posedge rst )
|
||||
begin
|
||||
if (r_en) dout <= ram_data[read_addr];
|
||||
if (w_en) ram_data[write_addr] <= din;
|
||||
if (rst)
|
||||
dout <= 0;
|
||||
else
|
||||
begin
|
||||
//if (r_en) dout <= ram_data[read_addr];
|
||||
dout <= ram_data[read_addr];
|
||||
if (w_en) ram_data[write_addr] <= din;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue