diff --git a/rtl/apple1.v b/rtl/apple1.v index 9c53844..0eef3e2 100644 --- a/rtl/apple1.v +++ b/rtl/apple1.v @@ -44,8 +44,11 @@ module apple1 #( input ps2_select, // Input to select the PS/2 keyboard instead of the UART // I/O interface to USB keyboard - inout usb_dm, // USB keyboard minus pin - inout usb_dp, // USB keyboard plus pin + input usb_dm_in, // USB keyboard minus pin + input usb_dp_in, // USB keyboard plus pin + output usb_en, + output usb_dm_out, // USB keyboard minus pin + output usb_dp_out, // USB keyboard plus pin // Outputs to VGA display output vga_h_sync, // hozizontal VGA sync pulse @@ -235,19 +238,30 @@ module apple1 #( ); // USB keyboard interface - wire [7:0] ukp_dout; + reg [7:0] ukp_dout; + wire [7:0] ukp_d; wire usb_int; ukp my_ukp( .clk25(clk25), .clkusb(clkusb), .rst(rst), - .usb_dm(usb_dm), - .usb_dp(usb_dp), + .usb_en(usb_en), + .usb_dm_in(usb_dm_in), + .usb_dp_in(usb_dp_in), + .usb_dm_out(usb_dm_out), + .usb_dp_out(usb_dp_out), .record_n(usb_int), .kbd_adr(ab[3:0]), - .kbd_data(ukp_dout) + .kbd_data(ukp_d), + .debug(debug) ); + always @(posedge clk25) + begin + if (usb_int) + ukp_dout <= ukp_d; + end + // Handle font mode and foreground and background // colours. This so isn't Apple One authentic, but // it can't hurt to have some fun. :D diff --git a/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v b/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v index 8791a29..6b4933e 100644 --- a/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v +++ b/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v @@ -130,6 +130,28 @@ module apple1_top #( always @(posedge ps2_toggle) ps2_select <= ~ps2_select; + wire usb_en; + wire usb_dm_in, usb_dp_in; + wire usb_dm_out, usb_dp_out; + SB_IO #( + .PIN_TYPE(6'b101001), + .PULLUP(1'b1) + ) tm_dm_io ( + .PACKAGE_PIN(usb_dm), + .OUTPUT_ENABLE(usb_en), + .D_IN_0(usb_dm_in), + .D_OUT_0(usb_dm_out) + ); + SB_IO #( + .PIN_TYPE(6'b101001), + .PULLUP(1'b1) + ) tm_dp_io ( + .PACKAGE_PIN(usb_dp), + .OUTPUT_ENABLE(usb_en), + .D_IN_0(usb_dp_in), + .D_OUT_0(usb_dp_out) + ); + ////////////////////////////////////////////////////////////////////////// // Core of system @@ -150,8 +172,11 @@ module apple1_top #( .ps2_clk(ps2__clk), .ps2_din(ps2__din), .ps2_select(ps2_select), - .usb_dm(usb_dm), - .usb_dp(usb_dp), + .usb_en(usb_en), + .usb_dm_in(usb_dm_in), + .usb_dp_in(usb_dp_in), + .usb_dm_out(usb_dm_out), + .usb_dp_out(usb_dp_out), .vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync), .vga_red(vga_red), diff --git a/rtl/ukp/ukp.v b/rtl/ukp/ukp.v index 7b39cec..27d66ef 100644 --- a/rtl/ukp/ukp.v +++ b/rtl/ukp/ukp.v @@ -2,8 +2,11 @@ module ukp( clk25, clkusb, rst, - usb_dm, - usb_dp, + usb_en, + usb_dm_in, + usb_dm_out, + usb_dp_in, + usb_dp_out, record_n, kbd_adr, kbd_data @@ -11,10 +14,13 @@ module ukp( input clk25; input clkusb; input rst; - output record_n; - inout usb_dm; - inout usb_dp; + input usb_dm_in; + input usb_dp_in; input [3:0] kbd_adr; + output usb_en; + output usb_dm_out; + output usb_dp_out; + output record_n; output [7:0] kbd_data; parameter S_OPCODE = 0; @@ -23,22 +29,22 @@ module ukp( parameter S_B0 = 3; parameter S_B1 = 4; - parameter LDI = 4'b0001; - parameter START = 4'b0010; + parameter I_LDI = 4'b0001; + parameter I_START = 4'b0010; - parameter OUT0 = 4'b0100; - parameter OUT1 = 4'b0101; - parameter OUT2 = 4'b0110; - parameter HZ = 4'b0111; + parameter I_OUT0 = 4'b0100; + parameter I_OUT1 = 4'b0101; + parameter I_OUT2 = 4'b0110; + parameter I_HZ = 4'b0111; - parameter BZ = 4'b1000; - parameter BC = 4'b1001; - parameter BNAK = 4'b1010; - parameter DJNZ = 4'b1011; + parameter I_BZ = 4'b1000; + parameter I_BC = 4'b1001; + parameter I_BNAK = 4'b1010; + parameter I_DJNZ = 4'b1011; - parameter TOGGLE = 4'b1100; - parameter IN = 4'b1101; - parameter WAIT = 4'b1110; + parameter I_TOGGLE = 4'b1100; + parameter I_IN = 4'b1101; + parameter I_WAIT = 4'b1110; function sel4; input [1:0] sel; @@ -66,24 +72,24 @@ module ukp( wire [3:0] inst; wire sample; - reg connected = 0; - reg inst_ready = 0; - reg g = 0; - reg p = 0; - reg m = 0; - reg cond = 0; - reg nak = 0; - reg dm1 = 0; - reg bank = 0; - reg record1 = 0; - reg [2:0] state = 0; - reg [7:0] w = 0; - reg [9:0] pc = 0; - reg [2:0] timing = 0; - reg [3:0] tmp = 0; - reg [13:0] interval = 0; - reg [5:0] bitadr = 0; - reg [7:0] data = 0; + reg connected; + reg inst_ready; + reg g; + reg p; + reg m; + reg cond; + reg nak; + reg dm1; + reg bank; + reg record1; + reg [2:0] state; + reg [7:0] w; + reg [9:0] pc; + reg [2:0] timing; + reg [3:0] tmp; + reg [13:0] interval; + reg [5:0] bitadr; + reg [7:0] data; ukprom ukprom( .clk(clkusb), @@ -94,9 +100,9 @@ module ukp( wire interval_cy = interval == 12001; wire next = ~(state == S_OPCODE & ( ~inst[3] & inst[2] & timing != 0 | - ~inst[3] & ~inst[2] & inst[1] & usb_dm | + ~inst[3] & ~inst[2] & inst[1] & usb_dm_in | inst == 4'b1110 & ~interval_cy | - inst == 4'b1101 & (~sample | (usb_dp | usb_dm) & w != 1) + inst == 4'b1101 & (~sample | (usb_dp_in | usb_dm_in) & w != 1) )); wire branch = state == S_B1 & cond; wire record; @@ -132,19 +138,27 @@ module ukp( begin if (state == S_OPCODE) begin - if (inst == 4'b0001) state <= S_LDI0; - if (inst == 4'b1100) connected <= ~connected; + // set LDI + if (inst == I_LDI) state <= S_LDI0; + + // set connected + if (inst == I_TOGGLE) connected <= ~connected; + + // handle USB outputs when timing is 0 if (~inst[3] & inst[2] & timing == 0) begin g <= ~inst[1] | ~inst[0]; p <= ~inst[1] & inst[0]; m <= inst[1] & ~inst[0]; end + + // handle branching if (inst[3] & ~inst[2]) begin state <= S_B0; - cond <= sel4(inst[1:0], {~usb_dm, connected, nak, w != 1}); + cond <= sel4(inst[1:0], {~usb_dm_in, connected, nak, w != 1}); end + if (inst == 4'b1011 | inst == 4'b1101 & sample) w <= w - 1; end @@ -195,10 +209,10 @@ module ukp( if (sample) begin - if (bitadr == 8) nak <= usb_dm; + if (bitadr == 8) nak <= usb_dm_in; data[6:0] <= data[7:1]; - data[7] <= dm1 ~^ usb_dm; - dm1 <= usb_dm; + data[7] <= dm1 ~^ usb_dm_in; + dm1 <= usb_dm_in; bitadr <= bitadr + 1; end diff --git a/rtl/ukp/ukprom.v b/rtl/ukp/ukprom.v index 46f1701..f63a6c4 100644 --- a/rtl/ukp/ukprom.v +++ b/rtl/ukp/ukprom.v @@ -1,16 +1,9 @@ -module ukprom( - clk, - adr, - data -); +module ukprom(clk, adr, data); input clk; input [9:0] adr; output [3:0] data; - reg [3:0] data; - - always @(posedge clk) - begin + always @(posedge clk) begin case (adr) 10'h000: data <= 4'h1; 10'h001: data <= 4'h9; @@ -24,8 +17,13 @@ module ukprom( 10'h009: data <= 4'h0; 10'h00a: data <= 4'h0; 10'h00b: data <= 4'h1; +`ifdef SIM + 10'h00c: data <= 4'h2; + 10'h00d: data <= 4'h0; +`else 10'h00c: data <= 4'h8; 10'h00d: data <= 4'hc; +`endif 10'h00e: data <= 4'h0; 10'h00f: data <= 4'h0; 10'h010: data <= 4'he; @@ -34,16 +32,26 @@ module ukprom( 10'h013: data <= 4'h0; 10'h014: data <= 4'h4; 10'h015: data <= 4'h1; +`ifdef SIM + 10'h016: data <= 4'h1; + 10'h017: data <= 4'h0; +`else 10'h016: data <= 4'ha; 10'h017: data <= 4'h0; +`endif 10'h018: data <= 4'he; 10'h019: data <= 4'hb; 10'h01a: data <= 4'h6; 10'h01b: data <= 4'h0; 10'h01c: data <= 4'h7; 10'h01d: data <= 4'h1; +`ifdef SIM + 10'h01e: data <= 4'h1; + 10'h01f: data <= 4'h0; +`else 10'h01e: data <= 4'h8; 10'h01f: data <= 4'h2; +`endif 10'h020: data <= 4'he; 10'h021: data <= 4'h4; 10'h022: data <= 4'h4; diff --git a/tools/iverilog/apple1_files.txt b/tools/iverilog/apple1/apple1_files.txt similarity index 100% rename from tools/iverilog/apple1_files.txt rename to tools/iverilog/apple1/apple1_files.txt diff --git a/tools/iverilog/apple1_tb.v b/tools/iverilog/apple1/apple1_tb.v similarity index 100% rename from tools/iverilog/apple1_tb.v rename to tools/iverilog/apple1/apple1_tb.v diff --git a/tools/iverilog/run_testbench.bat b/tools/iverilog/apple1/run_testbench.bat similarity index 100% rename from tools/iverilog/run_testbench.bat rename to tools/iverilog/apple1/run_testbench.bat diff --git a/tools/iverilog/run_uart_tb.sh b/tools/iverilog/uart/run_uart_tb.sh similarity index 100% rename from tools/iverilog/run_uart_tb.sh rename to tools/iverilog/uart/run_uart_tb.sh diff --git a/tools/iverilog/uart_files.txt b/tools/iverilog/uart/uart_files.txt similarity index 100% rename from tools/iverilog/uart_files.txt rename to tools/iverilog/uart/uart_files.txt diff --git a/tools/iverilog/uart_tb.v b/tools/iverilog/uart/uart_tb.v similarity index 100% rename from tools/iverilog/uart_tb.v rename to tools/iverilog/uart/uart_tb.v diff --git a/tools/iverilog/ukp/Makefile b/tools/iverilog/ukp/Makefile new file mode 100644 index 0000000..d3ba37e --- /dev/null +++ b/tools/iverilog/ukp/Makefile @@ -0,0 +1,19 @@ +TESTBENCH = ukp_tb + +SRC_DIR = ./ukp +SRC = $(SRC_DIR)/ukp.v \ + $(SRC_DIR)/ukpram.v \ + $(SRC_DIR)/ukprom.v \ + $(SRC_DIR)/keymap.v + +all: $(TESTBENCH).vcd + +display: $(TESTBENCH).vcd + open $(TESTBENCH).vcd + +$(TESTBENCH).vcd: $(TESTBENCH).out + vvp $(TESTBENCH).out + +$(TESTBENCH).out: $(TESTBENCH).v $(SRC) + iverilog -DSIM -g2005 -o $(TESTBENCH).out $(TESTBENCH).v $(SRC) + diff --git a/tools/iverilog/ukp/asukp.py b/tools/iverilog/ukp/asukp.py new file mode 100755 index 0000000..4e941ec --- /dev/null +++ b/tools/iverilog/ukp/asukp.py @@ -0,0 +1,132 @@ +#!/usr/bin/env python +""" +ukp compiler +""" + +import re + + +def putline(pcnt, code): + """ + output a line of verilog + """ + return "\t\t\t10'h{:03x}: data = 4'h{:01x};\n".format(pcnt, code) + + +def main(): + """ + main + """ + label_regex = re.compile(r'^\s*(\w+):') + labels = {} + pcnt = 0 + + instructions = { + 'nop': 0, + 'ldi': 1, + 'start': 2, + 'out0': 4, + 'out1': 5, + 'out2': 6, + 'hiz': 7, + 'bz': 8, + 'bc': 9, + 'bnak': 10, + 'djnz': 11, + 'toggle': 12, + 'in': 13, + 'wait': 14 + } + + with open('ukp.s', 'r') as src: + for line in src: + lbl = label_regex.match(line) + if lbl: + # found label + label = lbl.group(1) + + if label.startswith(';'): + # commented label + continue + + if label in labels: + print("{} already defined!".format(label)) + exit(1) + + pcnt = pcnt + 3 & ~3 + labels[label] = pcnt + + print('pc={:03x}\t{}'.format(pcnt, label)) + else: + tokens = line.split() + if not tokens or tokens[0].startswith(';'): + # skip empty lines + continue + + if tokens[0] not in instructions: + print('syntax error: {}'.format(tokens[0])) + exit(1) + + inst = instructions[tokens[0].lower()] + pcnt += 3 if (inst == 1 or inst >= 8 and inst < 12) else 1 + + src.seek(0) + + pcnt = 0 + with open('ukprom2.v', 'w') as dst: + dst.write("module ukprom(clk, adr, data);\n") + dst.write("\tinput clk;\n") + dst.write("\tinput [9:0] adr;\n") + dst.write("\toutput [3:0] data;\n") + dst.write("\treg [3:0] data;\n") + dst.write("\talways @(posedge clk) begin\n") + dst.write("\t\tcase (adr)\n") + + for line in src: + lbl = label_regex.match(line) + if lbl: + while pcnt & 3: + dst.write(putline(pcnt, 0)) + pcnt += 1 + + else: + tokens = line.split() + if not tokens or tokens[0].startswith(';'): + # skip empty lines + continue + + code = instructions[tokens[0].lower()] + + lbl = [k for k, v in labels.items() if v == pcnt] + if lbl: + dst.write("// >>>> {}\n".format(lbl.pop())) + + if code >= 8 and code < 12: + dst.write("// {}\n".format(tokens[1])) + + dst.write(putline(pcnt, code)) + pcnt += 1 + + if code == 1: + dst.write(putline(pcnt, int(tokens[1]) & 15)) + pcnt += 1 + dst.write(putline(pcnt, int(tokens[1]) >> 4)) + pcnt += 1 + + elif code >= 8 and code < 12: + if tokens[1] not in labels: + print("{} not defined".format(tokens[1])) + exit(1) + + addr = labels[tokens[1]] >> 2 + dst.write(putline(pcnt, addr & 15)) + pcnt += 1 + dst.write(putline(pcnt, addr >> 4)) + pcnt += 1 + + dst.write("\t\t\tdefault: data = 4'hX;\n") + dst.write("\t\tendcase\n\tend\nendmodule\n") + + +if __name__ == "__main__": + main() diff --git a/tools/iverilog/run_ukp_tb.sh b/tools/iverilog/ukp/run_ukp_tb.sh similarity index 100% rename from tools/iverilog/run_ukp_tb.sh rename to tools/iverilog/ukp/run_ukp_tb.sh diff --git a/tools/iverilog/ukp/ukp b/tools/iverilog/ukp/ukp new file mode 120000 index 0000000..603ce0d --- /dev/null +++ b/tools/iverilog/ukp/ukp @@ -0,0 +1 @@ +../../../rtl/ukp/ \ No newline at end of file diff --git a/tools/iverilog/ukp/ukp_tb.v b/tools/iverilog/ukp/ukp_tb.v new file mode 100644 index 0000000..7dddf31 --- /dev/null +++ b/tools/iverilog/ukp/ukp_tb.v @@ -0,0 +1,321 @@ + +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: Top level test bench for apple1_top +// +// Author.....: Niels A. Moseley +// Date.......: 26-1-2018 +// + +`timescale 1ns/100ps + +module ukp_tb; + + reg clk25; + reg clkusb; + reg rst; + reg [3:0] kbd_adr; + + wire usb_dm_out, usb_dp_out; + reg usb_dm_in, usb_dp_in; + + wire record_n; + wire [7:0] kbd_data; + + ////////////////////////////////////////////////////////////////////////// + // Setup dumping of data for inspection + + initial begin + + clk25 = 1'b0; + clkusb = 1'b0; + usb_dm_in = 1'b1; + usb_dp_in = 1'b0; + kbd_adr = 1'b0; + rst = 1'b1; + + $display("Starting..."); + $dumpfile("ukp_tb.vcd"); + $dumpvars; + #5 + rst = 1'b0; + + // switch off drive to allow seeing bus reset, real USB bus would have + // pull downs and device would have stronger pull up on the D- pin. To + // reset bus host yanks both D+ and D- to ground, in verilog hiz only + // way to see that. It's not real, but useful to see + #6097910.3 + usb_dm_in = 1'b0; // K -- SYNC + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // K -- + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J -- ACK 0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J 1 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K 0 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J 0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J 1 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K 0 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // K 1 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // K -- 1 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // -- SE0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // -- SE0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + + #33776.2 + usb_dm_in = 1'b0; // K -- SYNC + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // K -- + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J -- NACK 0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J 1 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K 0 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // J 1 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // J 1 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // K 0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // K 1 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K -- 0 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // -- SE0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // -- SE0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + + #33776.2 + usb_dm_in = 1'b0; // K -- SYNC + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // K -- + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // K -- DATA0 1 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // K 1 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // J 0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J 1 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K 0 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // K 0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // K 1 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // K -- 0 + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; // -- CRC + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b1; + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; + usb_dp_in = 1'b1; + #667.2 + usb_dm_in = 1'b0; // -- SE0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b0; // -- SE0 + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + #667.2 + usb_dm_in = 1'b1; // J + usb_dp_in = 1'b0; + + #1500000 $display("Stopping..."); + $finish; + end + + ////////////////////////////////////////////////////////////////////////// + // Clock + // + always + #20 clk25 = !clk25; + + always + #41.665 clkusb <= !clkusb; + + ////////////////////////////////////////////////////////////////////////// + // Core of system + ukp my_ukp ( + .clk25(clk25), + .clkusb(clkusb), + .rst(rst), + .usb_dm_in(usb_dm_in), + .usb_dp_in(usb_dp_in), + .usb_dm_out(usb_dm_out), + .usb_dp_out(usb_dp_out), + .record_n(record_n), + .kbd_adr(kbd_adr), + .kbd_data(kbd_data) + ); + +endmodule diff --git a/tools/iverilog/ukp_files.txt b/tools/iverilog/ukp_files.txt deleted file mode 100644 index 8b02961..0000000 --- a/tools/iverilog/ukp_files.txt +++ /dev/null @@ -1,4 +0,0 @@ -../../rtl/ukp/ukp.v -../../rtl/ukp/ukprom.v -../../rtl/ukp/keymap.v -ukp_tb.v diff --git a/tools/iverilog/ukp_tb.v b/tools/iverilog/ukp_tb.v deleted file mode 100644 index a8e6800..0000000 --- a/tools/iverilog/ukp_tb.v +++ /dev/null @@ -1,104 +0,0 @@ - -// Licensed to the Apache Software Foundation (ASF) under one -// or more contributor license agreements. See the NOTICE file -// distributed with this work for additional information -// regarding copyright ownership. The ASF licenses this file -// to you under the Apache License, Version 2.0 (the -// "License"); you may not use this file except in compliance -// with the License. You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, -// software distributed under the License is distributed on an -// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -// KIND, either express or implied. See the License for the -// specific language governing permissions and limitations -// under the License. -// -// Description: Top level test bench for apple1_top -// -// Author.....: Niels A. Moseley -// Date.......: 26-1-2018 -// - -`timescale 1ns/1ps - -module ukp_tb; - - reg clk12; - reg rst, enable; - reg usb_dm_out, usb_dp_out; - reg [3:0] kbd_adr; - - inout usb_dm, usb_dp; - - wire usb_dm_in, usb_dp_in; - wire record_n; - wire [7:0] kbd_data; - - assign usb_dm = (enable) ? usb_dm_out : 1'bZ; - assign usb_dp = (enable) ? usb_dp_out : 1'bZ; - assign usb_dm_in = usb_dm; - assign usb_dp_in = usb_dp; - - ////////////////////////////////////////////////////////////////////////// - // Setup dumping of data for inspection - - initial begin - - clk12 = 1'b0; - enable = 1'b1; - usb_dm_out = 1'b0; - usb_dp_out = 1'b0; - kbd_adr = 1'b0; - rst = 1'b1; - - $display("Starting..."); - $dumpfile("ukp_tb.vcd"); - $dumpvars; - #5 - rst = 1'b0; - - #48000 - usb_dm_out = 1'b1; - #1000 - enable = 1'b0; - - #3267997 - usb_dm_out = 1'b1; - enable = 1'b1; - - #10 - usb_dm_out = 1'b0; - usb_dp_out = 1'b1; - #10 - usb_dm_out = 1'b1; - usb_dp_out = 1'b0; - #10 - usb_dm_out = 1'b0; - usb_dp_out = 1'b1; - - #50000 $display("Stopping..."); - $finish; - end - - ////////////////////////////////////////////////////////////////////////// - // Clock - - always - #2 clk12 = !clk12; - - ////////////////////////////////////////////////////////////////////////// - // Core of system - ukp my_ukp ( - .clk12(clk12), - .rst(rst), - .usb_dm(usb_dm), - .usb_dp(usb_dp), - .record_n(record_n), - .kbd_adr(kbd_adr), - .kbd_data(kbd_data) - ); - -endmodule diff --git a/tools/iverilog/run_vga_tb.sh b/tools/iverilog/vga/run_vga_tb.sh similarity index 100% rename from tools/iverilog/run_vga_tb.sh rename to tools/iverilog/vga/run_vga_tb.sh diff --git a/tools/iverilog/vga_files.txt b/tools/iverilog/vga/vga_files.txt similarity index 100% rename from tools/iverilog/vga_files.txt rename to tools/iverilog/vga/vga_files.txt diff --git a/tools/iverilog/vga_tb.v b/tools/iverilog/vga/vga_tb.v similarity index 100% rename from tools/iverilog/vga_tb.v rename to tools/iverilog/vga/vga_tb.v