From 2717184e713cc46e13a5edfaf5c676d94d364672 Mon Sep 17 00:00:00 2001 From: Alan Garfield Date: Mon, 29 Jan 2018 17:45:01 +1100 Subject: [PATCH] Added yosys support again, yay for FOSS! --- .gitignore | 1 + boards/ice40hx8k_yosys/Makefile | 64 ++++++++++++++++++++++++++++ boards/ice40hx8k_yosys/ice40hx8k.pcf | 1 + rtl/apple1.v | 30 ++++++------- rtl/boards/ice40hx8k/apple1_hx8k.v | 5 ++- rtl/ram.v | 12 ++++-- rtl/rom_basic.v | 12 ++++-- rtl/rom_wozmon.v | 10 +++-- 8 files changed, 105 insertions(+), 30 deletions(-) create mode 100644 boards/ice40hx8k_yosys/Makefile create mode 120000 boards/ice40hx8k_yosys/ice40hx8k.pcf diff --git a/.gitignore b/.gitignore index 20edbaa..8876fd5 100644 --- a/.gitignore +++ b/.gitignore @@ -7,3 +7,4 @@ synlog.tcl *.swp *_tb *.vcd +build diff --git a/boards/ice40hx8k_yosys/Makefile b/boards/ice40hx8k_yosys/Makefile new file mode 100644 index 0000000..6460870 --- /dev/null +++ b/boards/ice40hx8k_yosys/Makefile @@ -0,0 +1,64 @@ +DEVICE = hx8k +PIN_DEF=ice40hx8k.pcf + +SOURCEDIR = ../../rtl +BUILDDIR = build + +all: + @echo " To build: make apple1" + @echo " To program: make prog" + @echo "To build report: make report" + @echo " To clean up: make clean" + +dir: + mkdir -p $(BUILDDIR) + +# ------ TEMPLATES ------ +$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v + yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^ + +$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif + arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ + +$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc + icepack $^ $@ + +%.rpt: $(BUILDDIR)/%.asc + icetime -d $(DEVICE) -mtr $@ $< + +%_tb.vvp: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb.vvp + vvp -N $< +vcd=$@ + +# ------ APPLE 1 ------ +apple1: dir $(BUILDDIR)/apple1.bin +report: dir apple1.rpt + +$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc +$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif +$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \ + $(SOURCEDIR)/ram.v \ + $(SOURCEDIR)/rom_wozmon.v \ + $(SOURCEDIR)/rom_basic.v \ + $(SOURCEDIR)/cpu/arlet_6502.v \ + $(SOURCEDIR)/cpu/arlet/ALU.v \ + $(SOURCEDIR)/cpu/arlet/cpu.v \ + $(SOURCEDIR)/uart/uart.v \ + $(SOURCEDIR)/uart/async_tx_rx.v \ + $(SOURCEDIR)/ps2keyboard/ps2keyboard.v \ + $(SOURCEDIR)/boards/ice40hx8k/clock_pll.v \ + $(SOURCEDIR)/boards/ice40hx8k/apple1_hx8k.v + +apple1.rpt: $(BUILDDIR)/apple1.asc + +prog: dir $(BUILDDIR)/apple1.bin + iceprog -S $(filter-out $<,$^) + +# ------ HELPERS ------ +clean: + rm -rf build apple1.rpt + +.SECONDARY: +.PHONY: all clean prog iceprog diff --git a/boards/ice40hx8k_yosys/ice40hx8k.pcf b/boards/ice40hx8k_yosys/ice40hx8k.pcf new file mode 120000 index 0000000..b9e107e --- /dev/null +++ b/boards/ice40hx8k_yosys/ice40hx8k.pcf @@ -0,0 +1 @@ +../ice40hx8k/ice40hx8k.pcf \ No newline at end of file diff --git a/rtl/apple1.v b/rtl/apple1.v index b0de29b..234319a 100644 --- a/rtl/apple1.v +++ b/rtl/apple1.v @@ -1,20 +1,17 @@ module apple1( - input clk25, // 25 MHz master clock - input rst_n, // active low synchronous reset (needed for simulation) + input clk25, // 25 MHz master clock + input rst_n, // active low synchronous reset (needed for simulation) input uart_rx, output uart_tx, output uart_cts, - input ps2_clk, // PS/2 keyboard serial clock input - input ps2_din, // PS/2 keyboard serial data input + input ps2_clk, // PS/2 keyboard serial clock input + input ps2_din, // PS/2 keyboard serial data input - output [15:0] pc_monitor // spy for program counter / debugging + output [15:0] pc_monitor, // spy for program counter / debugging + input reset_button // allow a physical reset button ); - parameter RAM_FILENAME = "../../roms/ram.hex"; - parameter WOZ_FILENAME = "../../roms/wozmon.hex"; - parameter BASIC_FILENAME = "../../roms/basic.hex"; - ////////////////////////////////////////////////////////////////////////// // Registers and Wires @@ -89,7 +86,7 @@ module apple1( end end - assign reset = ~hard_reset; + assign reset = ~(hard_reset && reset_button); ////////////////////////////////////////////////////////////////////////// // 6502 @@ -120,7 +117,7 @@ module apple1( // RAM wire [7:0] ram_dout; - ram #(RAM_FILENAME) my_ram ( + ram my_ram( .clk(clk25), .address(ab[12:0]), .w_en(we & ram_cs), @@ -130,7 +127,7 @@ module apple1( // WozMon ROM wire [7:0] rom_dout; - rom_wozmon #(WOZ_FILENAME) my_rom_wozmon ( + rom_wozmon my_rom_wozmon( .clk(clk25), .address(ab[7:0]), .dout(rom_dout) @@ -138,7 +135,7 @@ module apple1( // Basic ROM wire [7:0] basic_dout; - rom_basic #(BASIC_FILENAME) my_rom_basic ( + rom_basic my_rom_basic( .clk(clk25), .address(ab[11:0]), .dout(basic_dout) @@ -150,9 +147,9 @@ module apple1( `ifdef SIM 100, 10, 2 // for simulation don't need real baud rates `else - 25000000, 115200, 8 + 25000000, 115200, 8 // 25MHz, 115200 baud, 8 times RX oversampling `endif - )my_uart ( + ) my_uart( .clk(clk25), .reset(reset), @@ -170,8 +167,7 @@ module apple1( // PS/2 keyboard interface wire [7:0] ps2_dout; - ps2keyboard keyboard - ( + ps2keyboard keyboard( .clk25(clk25), .reset(reset), .key_clk(ps2_clk), diff --git a/rtl/boards/ice40hx8k/apple1_hx8k.v b/rtl/boards/ice40hx8k/apple1_hx8k.v index 4f5b4b6..f4ff353 100644 --- a/rtl/boards/ice40hx8k/apple1_hx8k.v +++ b/rtl/boards/ice40hx8k/apple1_hx8k.v @@ -5,7 +5,7 @@ module apple1_top( output uart_tx, output uart_cts, output [15:0] led, - output [1:0] button + input [3:0] button ); wire clk25; @@ -29,7 +29,8 @@ module apple1_top( .uart_rx(uart_rx), .uart_tx(uart_tx), .uart_cts(uart_cts), - .pc_monitor(pc_monitor) + .pc_monitor(pc_monitor), + .reset_button(button[0]) ); endmodule diff --git a/rtl/ram.v b/rtl/ram.v index f5f9a0d..521844d 100644 --- a/rtl/ram.v +++ b/rtl/ram.v @@ -6,17 +6,21 @@ module ram( output reg [7:0] dout ); + `ifdef YOSYS + parameter RAM_FILENAME = "../../roms/ram.hex"; + `else parameter RAM_FILENAME = "../roms/ram.hex"; + `endif - reg [7:0] ram[0:8191]; + reg [7:0] ram_data[0:8191]; initial - $readmemh(RAM_FILENAME, ram, 0, 8191); + $readmemh(RAM_FILENAME, ram_data, 0, 8191); always @(posedge clk) begin - dout <= ram[address]; - if (w_en) ram[address] <= din; + dout <= ram_data[address]; + if (w_en) ram_data[address] <= din; end endmodule diff --git a/rtl/rom_basic.v b/rtl/rom_basic.v index 296b0c1..e37dbda 100644 --- a/rtl/rom_basic.v +++ b/rtl/rom_basic.v @@ -4,14 +4,18 @@ module rom_basic( output reg [7:0] dout ); - parameter ROM_FILENAME = "../roms/basic.hex"; + `ifdef YOSYS + parameter BASIC_FILENAME = "../../roms/basic.hex"; + `else + parameter BASIC_FILENAME = "../roms/basic.hex"; + `endif - reg [11:0] rom[0:4095]; + reg [7:0] rom_data[0:4095]; initial - $readmemh(ROM_FILENAME, rom, 0, 4095); + $readmemh(BASIC_FILENAME, rom_data, 0, 4095); always @(posedge clk) - dout <= rom[address]; + dout <= rom_data[address]; endmodule diff --git a/rtl/rom_wozmon.v b/rtl/rom_wozmon.v index 46efb84..61f8d2d 100644 --- a/rtl/rom_wozmon.v +++ b/rtl/rom_wozmon.v @@ -4,15 +4,19 @@ module rom_wozmon( output reg [7:0] dout ); + `ifdef YOSYS + parameter ROM_FILENAME = "../../roms/wozmon.hex"; + `else parameter ROM_FILENAME = "../roms/wozmon.hex"; + `endif - reg [7:0] rom[0:255]; + reg [7:0] rom_data[0:255]; initial - $readmemh(ROM_FILENAME, rom, 0, 255); + $readmemh(ROM_FILENAME, rom_data, 0, 255); always @(posedge clk) - dout <= rom[address]; + dout <= rom_data[address]; endmodule