Apple-1-HW/verilog-apple-one
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DE0

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This commit is contained in:
Niels Moseley 2018-02-07 17:04:40 +01:00
parent c1942d5d14
commit 2ae6d8a867
2 changed files with 29 additions and 2 deletions
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29
rtl/boards/terasic_de0/apple1_de0_top.v
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@ -36,8 +36,15 @@ module apple1_de0_top(
output [6:0] HEX1_D,
output [6:0] HEX2_D,
output [6:0] HEX3_D,
input PS2_KBCLK,
input PS2_KBDAT
input PS2_KBDAT,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
);
//////////////////////////////////////////////////////////////////////////
@ -51,6 +58,8 @@ module apple1_de0_top(
clk25 <= ~clk25;
end
wire vga_bit;
//////////////////////////////////////////////////////////////////////////
// Core of system
apple1 apple1_top(
@ -61,9 +70,19 @@ module apple1_de0_top(
.uart_cts(UART_CTS),
.ps2_clk(PS2_KBCLK),
.ps2_din(PS2_KBDAT),
.vga_h_sync(VGA_HS),
.vga_v_sync(VGA_VS),
.vga_red(vga_bit),
//.vga_grn(vga_bit),
//.vga_blu(vga_bit),
.clr_screen_btn(~BUTTON[1]),
.pc_monitor(pc_monitor)
);
assign VGA_R[3:0] = vga_bit ? 4'b1111 : 4'b0000;
assign VGA_G[3:0] = vga_bit ? 4'b1111 : 4'b0000;
assign VGA_B[3:0] = vga_bit ? 4'b1111 : 4'b0000;
//////////////////////////////////////////////////////////////////////////
// Display 6502 address on 7-segment displays
@ -95,4 +114,12 @@ module apple1_de0_top(
.display_out(HEX3_D)
);
reg [15:0] cnt;
always @(posedge vga_bit)
begin
cnt <= cnt + 1;
end
assign LEDG = cnt[7:0];
endmodule

2
rtl/ps2keyboard/ps2keyboard.v
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@ -208,7 +208,7 @@ begin
8'h4E: ascii <= "-";
8'h55: ascii <= "=";
8'h5D: ascii <= "\\ ";
8'h5D: ascii <= "\\ "; // extra spaced needed by Quartus
8'h66: ascii <= 8'd8; // backspace
8'h29: ascii <= " ";