mirror of
https://github.com/alangarf/apple-one.git
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Merge pull request #10 from al177/master
Add UPDuino (iCE40UP5K) support to apple-one
This commit is contained in:
commit
3505ff20fc
80
boards/ice40up5k_yosys/Makefile
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boards/ice40up5k_yosys/Makefile
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DEVICE = 5k
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PACKAGE = sg48
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FREQ_OSC = 48
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FREQ_PLL = 25
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PIN_DEF=ice40up5k.pcf
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SOURCEDIR = ../../rtl
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BUILDDIR = build
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PLL=$(BUILDDIR)/pll.sv
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all: $(PLL) apple1 prog
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info:
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@echo " To build: make apple1"
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@echo " To program: make prog"
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@echo "To build report: make report"
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@echo " To clean up: make clean"
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dir:
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mkdir -p $(BUILDDIR)
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# ------ TEMPLATES ------
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$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
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yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^
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$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
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arachne-pnr -d $(DEVICE) -P $(PACKAGE) -o $@ -p $^
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$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
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icepack $^ $@
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%.rpt: $(BUILDDIR)/%.asc
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icetime -d $(DEVICE) -P $(PACKAGE) -c $(FREQ_PLL) -mtr $@ $<
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%_tb.vvp: %_tb.v %.v
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iverilog -o $@ $^
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%_tb.vcd: %_tb.vvp
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vvp -N $< +vcd=$@
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$(PLL):
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icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
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# ------ APPLE 1 ------
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apple1: dir $(BUILDDIR)/apple1.bin
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report: dir apple1.rpt
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$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
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$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
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$(BUILDDIR)/apple1.blif: $(BUILDDIR)/pll.sv \
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$(SOURCEDIR)/apple1.v \
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$(SOURCEDIR)/clock.v \
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$(SOURCEDIR)/pwr_reset.v \
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$(SOURCEDIR)/ram.v \
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$(SOURCEDIR)/rom_wozmon.v \
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$(SOURCEDIR)/rom_basic.v \
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$(SOURCEDIR)/cpu/arlet_6502.v \
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$(SOURCEDIR)/cpu/arlet/ALU.v \
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$(SOURCEDIR)/cpu/arlet/cpu.v \
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$(SOURCEDIR)/uart/uart.v \
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$(SOURCEDIR)/uart/async_tx_rx.v \
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$(SOURCEDIR)/vga/vga.v \
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$(SOURCEDIR)/vga/vram.v \
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$(SOURCEDIR)/vga/font_rom.v \
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$(SOURCEDIR)/ps2keyboard/debounce.v \
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$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
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$(SOURCEDIR)/boards/ice40up5k/apple1_up5k.v
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apple1.rpt: $(BUILDDIR)/apple1.asc
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prog: dir $(BUILDDIR)/apple1.bin
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iceprog -S $(filter-out $<,$^)
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# ------ HELPERS ------
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clean:
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rm -rf build apple1.rpt
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.SECONDARY:
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.PHONY: all info clean prog iceprog
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31
boards/ice40up5k_yosys/README.md
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boards/ice40up5k_yosys/README.md
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# iCE40UP5K support
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This board directory builds for the iCE40UP5K in the QFN48 (SG48) package. iCE40UP5K SG48 is the part used on the [Gnarly Grey UPDuino Mini board](https://gnarlygrey.atspace.cc/development-platform.html).
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## Peripheral support
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So far only UART is tested and supported. Three bits of the PC monitor bus are mapped to the dedicated LED drivers to give some indication of the currently running code.
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VGA is brought out to pins but have not been tested.
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PS/2, button, and TM1638 front panel are not supported.
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At this time, all ROM and RAM are mapped as block RAM, and arachne-pnr reports that 28/30 BRAMs are utilized. If larger ROMs or more RAM is needed, RAM should be moved to SPRAM instead.
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The on-chip oscillator and PLL are used to generate the 25MHz clock used by the design.
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See the .pcf for pin connections. Note that the iCE40UP5K pin numbers in the .pcf correspond to the UPDuino pin silkscreen labels.
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## Building
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Install a recent IceStorm toolchain, and:
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make clean all
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## Use
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Flash using your method of choice. Attach a 3.3V serial connection to uart_tx (output to PC) and uart_rx (input from PC). Start a terminal at 115200,n,8,1.
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Toggling CRESET_B restarts to the Woz monitor.
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The Woz monitor is a simple hex debugger. To run BASIC, type: "E000R". Note that both BASIC and the monitor require commands to be input as caps.
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19
boards/ice40up5k_yosys/ice40up5k.pcf
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boards/ice40up5k_yosys/ice40up5k.pcf
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# For the iCE40UP-5K UPDuino board
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### UART (FTDI Channel B)
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set_io uart_rx 12
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set_io uart_tx 21
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set_io uart_cts 13
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### Breakout Board LEDs
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set_io red_led 41
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set_io green_led 40
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set_io blue_led 39
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### VGA Display
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set_io vga_h_sync 18
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set_io vga_v_sync 11
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set_io vga_red 10
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set_io vga_grn 9
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set_io vga_blu 6
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rtl/boards/ice40up5k/apple1_up5k.v
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rtl/boards/ice40up5k/apple1_up5k.v
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple 1 implementation for the iCE40HX8K dev
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// board.
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//
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// Author.....: Alan Garfield
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// Date.......: 26-1-2018
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//
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module apple1_top(
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// I/O interface to computer
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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output uart_cts, // clear to send flag to computer
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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output reg vga_red, // red VGA signal
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output reg vga_grn, // green VGA signal
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output reg vga_blu, // blue VGA signal
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// Tricolor LED on the UPDuino
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output red_led,
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output green_led,
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output blue_led
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);
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wire [15:0] leds;
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assign red_led = ~leds[9];
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assign green_led = ~leds[8];
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assign blue_led = ~leds[7];
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wire clk25;
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wire clk;
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wire clk25;
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SB_HFOSC inthosc (
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.CLKHFPU(1'b1),
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.CLKHFEN(1'b1),
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.CLKHF(clk)
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);
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pll pll(
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.clock_in(clk),
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.clock_out(clk25),
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);
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// apple one main system
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apple1 my_apple1(
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.clk25(clk25),
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.rst_n(1'b1),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts),
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.clr_screen_btn(1'b0),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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.vga_grn(vga_grn),
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.vga_blu(vga_blu),
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.pc_monitor(leds),
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.ps2_select(1'b0), // no ps2 keyboard right now
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);
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endmodule
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