Initial port to olimex ice40hx8k with ice-40io

ps2 will be added when someone donates a ps2 keyboard

boards/olimex_ice40hx8k_evb_yosys/Makefile

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+DEVICE = hx8k
+PIN_DEF=ice40hx8k.pcf
+
+SOURCEDIR = ../../rtl
+BUILDDIR = build
+
+all: apple1 prog
+
+info:
+	@echo "       To build: make apple1"
+	@echo "     To program: make prog"
+	@echo "To build report: make report"
+	@echo "    To clean up: make clean"
+
+dir:
+	mkdir -p $(BUILDDIR)
+
+# ------ TEMPLATES ------
+$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
+	yosys -q  -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^
+
+$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
+	arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^
+
+$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
+	icepack $^ $@
+
+%.rpt: $(BUILDDIR)/%.asc
+	icetime -d $(DEVICE) -mtr $@ $<
+
+%_tb.vvp: %_tb.v %.v
+	iverilog -o $@ $^
+
+%_tb.vcd: %_tb.vvp
+	vvp -N $< +vcd=$@
+
+# ------ APPLE 1 ------
+apple1: dir $(BUILDDIR)/apple1.bin
+report: dir apple1.rpt
+
+$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
+$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
+$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
+	$(SOURCEDIR)/clock.v \
+	$(SOURCEDIR)/pwr_reset.v \
+	$(SOURCEDIR)/ram.v \
+	$(SOURCEDIR)/rom_wozmon.v \
+	$(SOURCEDIR)/rom_basic.v \
+	$(SOURCEDIR)/cpu/arlet_6502.v \
+	$(SOURCEDIR)/cpu/arlet/ALU.v \
+	$(SOURCEDIR)/cpu/arlet/cpu.v \
+	$(SOURCEDIR)/uart/uart.v \
+	$(SOURCEDIR)/uart/async_tx_rx.v \
+	$(SOURCEDIR)/vga/vga.v \
+	$(SOURCEDIR)/vga/vram.v \
+	$(SOURCEDIR)/vga/font_rom.v \
+	$(SOURCEDIR)/ps2keyboard/debounce.v \
+	$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
+	$(SOURCEDIR)/boards/olimex_ice40hx8k/pll.v \
+	$(SOURCEDIR)/boards/olimex_ice40hx8k/apple1_hx8k.v
+
+apple1.rpt: $(BUILDDIR)/apple1.asc
+
+prog: dir $(BUILDDIR)/apple1.bin
+	iceprogduino  $(filter-out $<,$^)
+
+# ------ HELPERS ------
+clean:
+	rm -rf build apple1.rpt
+
+.SECONDARY:
+.PHONY: all info clean prog iceprog

boards/olimex_ice40hx8k_evb_yosys/ice40hx8k.pcf

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+# For the olimex-iCE40HX8K-EVB
+# plus iCE40-IO expansion board with vga and ps2
+
+## System Clock 100Mhz
+set_io clk J3
+
+### UART
+set_io uart_rx E4
+set_io uart_tx B2
+set_io uart_cts F5
+
+
+set_io button[0] K11
+set_io button[1] P13
+
+### VGA Display
+set_io vga_v_sync H2
+set_io vga_h_sync J4
+
+set_io vga_r[0] E3
+set_io vga_r[1] H5
+set_io vga_r[2] F3
+set_io vga_g[0] H3
+set_io vga_g[1] F2
+set_io vga_g[2] H6
+set_io vga_b[0] F1
+set_io vga_b[1] H4
+set_io vga_b[2] G2

rtl/boards/olimex_ice40hx8k/apple1_hx8k.v

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+// Licensed to the Apache Software Foundation (ASF) under one
+// or more contributor license agreements.  See the NOTICE file
+// distributed with this work for additional information
+// regarding copyright ownership.  The ASF licenses this file
+// to you under the Apache License, Version 2.0 (the
+// "License"); you may not use this file except in compliance
+// with the License.  You may obtain a copy of the License at
+//
+//   http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// software distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+// Description: Apple 1 implementation for the iCE40HX8K dev
+//              board.
+//
+// Author.....: Alan Garfield
+// Date.......: 26-1-2018
+//
+
+module apple1_top(
+    input  clk,             // 100 MHz board clock
+
+    // I/O interface to computer
+    input  uart_rx,         // asynchronous serial data input from computer
+    output uart_tx,         // asynchronous serial data output to computer
+    output uart_cts,        // clear to send flag to computer
+
+    // Outputs to VGA display
+    output vga_h_sync,          // hozizontal VGA sync pulse
+    output vga_v_sync,          // vertical VGA sync pulse
+    output [2:0] vga_r,         // red VGA signal
+    output [2:0] vga_g,         // green VGA signal
+    output [2:0] vga_b,         // blue VGA signal
+
+    input [1:0] button
+);
+
+    wire clk25;
+
+    pll pll(.clock_in(clk),
+        .clock_out(clk25),
+    );
+
+    wire vga_bit;
+
+    // set the monochrome base colour here..
+    assign vga_r[2:0] = vga_bit ? 3'b100 : 3'b000;
+    assign vga_g[2:0] = vga_bit ? 3'b111 : 3'b000;
+    assign vga_b[2:0] = vga_bit ? 3'b100 : 3'b000;
+
+    // apple one main system
+    apple1 my_apple1(
+        .clk25(clk25),
+        .rst_n(button[0]),
+        .uart_rx(uart_rx),
+        .uart_tx(uart_tx),
+        .uart_cts(uart_cts),
+        .clr_screen_btn(0),
+        .vga_h_sync(vga_h_sync),
+        .vga_v_sync(vga_v_sync),
+        .vga_red(vga_bit),
+        .ps2_select(1'b0),
+    );
+endmodule

rtl/boards/olimex_ice40hx8k/pll.v

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+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:       100.000 MHz
+ * Requested output frequency:   25.000 MHz
+ * Achieved output frequency:    25.000 MHz
+ */
+
+module pll(
+	input  clock_in,
+	output clock_out,
+	output locked
+	);
+
+SB_PLL40_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0000),		// DIVR =  0
+		.DIVF(7'b0000111),	// DIVF =  7
+		.DIVQ(3'b101),		// DIVQ =  5
+		.FILTER_RANGE(3'b101)	// FILTER_RANGE = 5
+	) uut (
+		.LOCK(locked),
+		.RESETB(1'b1),
+		.BYPASS(1'b0),
+		.REFERENCECLK(clock_in),
+		.PLLOUTCORE(clock_out)
+		);
+
+endmodule