Apple-1-HW/verilog-apple-one
1
0
Fork 0
mirror of https://github.com/alangarf/apple-one.git synced 2024-06-14 23:29:36 +00:00
Code Issues Projects Releases Wiki Activity

Merge pull request #1 from alangarf/alangarf-readme

Browse Source 
Updated readme
This commit is contained in:
Alan Garfield 2018-01-12 14:42:57 +11:00 committed by GitHub
commit 50d80bedcd
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -2,6 +2,8 @@
This is a basic implementation of the original Apple 1 in Verilog for an iCE40HX FPGA. It can run the Apple 1 WozMon and Integer Basic via the serial USB interface which is available on the iCE40HX8K-B-EVN breakout board. This makes this a very compact little set up. There is no reason this cannot be implemented for other FPGAs with very little work.
![iCE40HX8K](https://github.com/alangarf/apple-one/raw/master/media/iCE40HX8K-breakout.png)
This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project where he built a 6502 CPU core in Verilog using the netlist from the Visual 6502 project. Amazing stuff, and so far seems to work perfectly. Also many special thanks to ["sbprojects.com"](https://www.sbprojects.com/projects/apple1/index.php) for the wealth of information I gleaned from there.
## Memory Map

BIN
media/iCE40HX8K-breakout.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 39 KiB