Apple-1-HW
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verilog-apple-one
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Fix syntax error on apple1 declaration by adding missing closing parentheses 

yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif build/apple1.blif" ../../../rtl/apple1.v build/pll.sv ../../../rtl/clock.v ../../../rtl/pwr_reset.v ../../../rtl/ram.v ../../../rtl/rom_wozmon.v ../../../rtl/rom_basic.v ../../../rtl/cpu/arlet_6502.v ../../../rtl/cpu/arlet/ALU.v ../../../rtl/cpu/arlet/cpu.v ../../../rtl/uart/uart.v ../../../rtl/uart/async_tx_rx.v ../../../rtl/vga/vga.v ../../../rtl/vga/vram.v ../../../rtl/vga/font_rom.v ../../../rtl/ps2keyboard/debounce.v ../../../rtl/ps2keyboard/ps2keyboard.v ../../../rtl/boards/upduino/apple1_up5k.v
Warning: Replacing memory \AXYS with list of registers. See ../../../rtl/cpu/arlet/cpu.v:541
ERROR: Parser error in line ../../../rtl/boards/upduino/apple1_up5k.v:76: syntax error, unexpected TOK_ID, expecting ',' or ')'
Makefile:26: recipe for target 'build/apple1.blif' failed
make: *** [build/apple1.blif] Error 1
This commit is contained in:
Steve White 2018-05-05 12:59:16 -07:00
parent ddbbae966f
commit 59bbb91a8d
1 changed files with 1 additions and 1 deletions
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2
rtl/boards/upduino/apple1_up5k.v
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@ -73,7 +73,7 @@ module apple1_top #(
.RAM_FILENAME (RAM_FILENAME),
.VRAM_FILENAME (VRAM_FILENAME),
.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
my_apple1(
) my_apple1(
.clk25(clk25),
.rst_n(1'b1),
.uart_rx(uart_rx),