Apple-1-HW/verilog-apple-one
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Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined

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This commit is contained in:
Niels Moseley 2018-01-27 01:21:47 +01:00
parent f19344cf58
commit 5e3f065223
2 changed files with 11 additions and 1 deletions
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10
iverilog/apple1_top_tb.v
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@ -32,11 +32,21 @@ module apple1_top_tb;
// Setup dumping of data for inspection
initial begin
force core_top.my_cpu.DIHOLD = 0;
force core_top.my_cpu.ALU.OUT = 0;
force core_top.my_cpu.PC = 0;
force core_top.my_cpu.ALU.temp_logic = 0;
clk25 = 1'b0;
uart_rx = 1'b0;
rst_n = 1'b0;
#40 rst_n = 1'b1;
release core_top.my_cpu.DIHOLD;
release core_top.my_cpu.PC;
release core_top.my_cpu.ALU.OUT;
release core_top.my_cpu.ALU.temp_logic;
$display("Starting...");
$dumpfile("apple1_top_tb.vcd");
$dumpvars;

2
rtl/apple1_top.v
View File

@ -80,7 +80,7 @@ module top(
if (rst_n == 1'b0)
begin
reset_cnt <= 6'b0;
//hard_reset <= 1'b0; we should init hard_reset here too..
hard_reset <= 1'b0;
end
else if (cpu_clken)
begin