Apple-1-HW/verilog-apple-one
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Updated Terasic DE0 target to new dir format

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This commit is contained in:
Niels Moseley 2018-02-11 22:48:00 +01:00
parent 7f18c17152
commit 61f9fc4937
9 changed files with 28 additions and 28 deletions
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0
boards/terasic_de0/apple-one.pin → boards/terasic_de0/Quartus/apple-one.pin
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0
boards/terasic_de0/apple-one.qpf → boards/terasic_de0/Quartus/apple-one.qpf
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36
boards/terasic_de0/apple-one.qsf → boards/terasic_de0/Quartus/apple-one.qsf
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@ -367,23 +367,23 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VERILOG_FILE ../../rtl/ps2keyboard/debounce.v
set_global_assignment -name VERILOG_FILE ../../rtl/vga/vram.v
set_global_assignment -name VERILOG_FILE ../../rtl/vga/vga.v
set_global_assignment -name VERILOG_FILE ../../rtl/vga/font_rom.v
set_global_assignment -name VERILOG_FILE ../../rtl/pwr_reset.v
set_global_assignment -name VERILOG_FILE ../../rtl/clock.v
set_global_assignment -name VERILOG_FILE ../../rtl/rom_basic.v
set_global_assignment -name VERILOG_FILE ../../rtl/ps2keyboard/ps2keyboard.v
set_global_assignment -name VERILOG_FILE ../../rtl/boards/terasic_de0/segmentdisplay.v
set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/cpu.v
set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/ALU.v
set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet_6502.v
set_global_assignment -name VERILOG_FILE ../../rtl/apple1.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ps2keyboard/debounce.v
set_global_assignment -name VERILOG_FILE ../../../rtl/vga/vram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/vga/vga.v
set_global_assignment -name VERILOG_FILE ../../../rtl/vga/font_rom.v
set_global_assignment -name VERILOG_FILE ../../../rtl/pwr_reset.v
set_global_assignment -name VERILOG_FILE ../../../rtl/clock.v
set_global_assignment -name VERILOG_FILE ../../../rtl/rom_basic.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ps2keyboard/ps2keyboard.v
set_global_assignment -name VERILOG_FILE ../../../rtl/boards/terasic_de0/segmentdisplay.v
set_global_assignment -name VERILOG_FILE ../../../rtl/cpu/arlet/cpu.v
set_global_assignment -name VERILOG_FILE ../../../rtl/cpu/arlet/ALU.v
set_global_assignment -name VERILOG_FILE ../../../rtl/cpu/arlet_6502.v
set_global_assignment -name VERILOG_FILE ../../../rtl/apple1.v
set_global_assignment -name SDC_FILE "apple-one.sdc"
set_global_assignment -name VERILOG_FILE ../../rtl/boards/terasic_de0/apple1_de0_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart/async_tx_rx.v
set_global_assignment -name VERILOG_FILE ../../rtl/rom_wozmon.v
set_global_assignment -name VERILOG_FILE ../../rtl/ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/boards/terasic_de0/apple1_de0_top.v
set_global_assignment -name VERILOG_FILE ../../../rtl/uart/uart.v
set_global_assignment -name VERILOG_FILE ../../../rtl/uart/async_tx_rx.v
set_global_assignment -name VERILOG_FILE ../../../rtl/rom_wozmon.v
set_global_assignment -name VERILOG_FILE ../../../rtl/ram.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

0
boards/terasic_de0/apple-one.sdc → boards/terasic_de0/Quartus/apple-one.sdc
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4
rtl/ram.v
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@ -31,9 +31,9 @@ module ram(
);
`ifdef SIM
parameter RAM_FILENAME = "../roms/ram.hex";
`else
parameter RAM_FILENAME = "../../roms/ram.hex";
`else
parameter RAM_FILENAME = "../../../roms/ram.hex";
`endif
reg [7:0] ram_data[0:8191];

4
rtl/rom_basic.v
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@ -29,9 +29,9 @@ module rom_basic(
);
`ifdef SIM
parameter BASIC_FILENAME = "../roms/basic.hex";
`else
parameter BASIC_FILENAME = "../../roms/basic.hex";
`else
parameter BASIC_FILENAME = "../../../roms/basic.hex";
`endif
reg [7:0] rom_data[0:4095];

4
rtl/rom_wozmon.v
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@ -29,9 +29,9 @@ module rom_wozmon(
);
`ifdef SIM
parameter ROM_FILENAME = "../roms/wozmon.hex";
`else
parameter ROM_FILENAME = "../../roms/wozmon.hex";
`else
parameter ROM_FILENAME = "../../../roms/wozmon.hex";
`endif
reg [7:0] rom_data[0:255];

4
rtl/vga/font_rom.v
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@ -34,9 +34,9 @@ module font_rom(
);
`ifdef SIM
parameter ROM_FILENAME = "../roms/vga_font_bitreversed.hex";
`else
parameter ROM_FILENAME = "../../roms/vga_font_bitreversed.hex";
`else
parameter ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex";
`endif
reg [7:0] rom[0:1023];

4
rtl/vga/vram.v
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@ -33,9 +33,9 @@ module vram(
);
`ifdef SIM
parameter RAM_FILENAME = "../roms/vga_vram.bin";
`else
parameter RAM_FILENAME = "../../roms/vga_vram.bin";
`else
parameter RAM_FILENAME = "../../../roms/vga_vram.bin";
`endif
reg [5:0] ram_data[0:2047];