From 657fbc69b47650735acc1a068b711ee671089c9e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 11 Feb 2018 14:38:01 +0100 Subject: [PATCH] Support for TinyFPGA B2 with computer board --- boards/tinyfpga_yosys/Makefile | 72 ++++++++++++++++++++++ boards/tinyfpga_yosys/apple1_hx8k.v | 92 +++++++++++++++++++++++++++++ boards/tinyfpga_yosys/clock_pll.v | 38 ++++++++++++ boards/tinyfpga_yosys/tinyfpga.pcf | 29 +++++++++ 4 files changed, 231 insertions(+) create mode 100644 boards/tinyfpga_yosys/Makefile create mode 100644 boards/tinyfpga_yosys/apple1_hx8k.v create mode 100644 boards/tinyfpga_yosys/clock_pll.v create mode 100644 boards/tinyfpga_yosys/tinyfpga.pcf diff --git a/boards/tinyfpga_yosys/Makefile b/boards/tinyfpga_yosys/Makefile new file mode 100644 index 0000000..a0005a1 --- /dev/null +++ b/boards/tinyfpga_yosys/Makefile @@ -0,0 +1,72 @@ +DEVICE = lp8k +PIN_DEF=tinyfpga.pcf + +SOURCEDIR = ../../rtl +BUILDDIR = build + +all: apple1 prog + +info: + @echo " To build: make apple1" + @echo " To program: make prog" + @echo "To build report: make report" + @echo " To clean up: make clean" + +dir: + mkdir -p $(BUILDDIR) + +# ------ TEMPLATES ------ +$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v + yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^ + +$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif + arachne-pnr -d 8k -P cm81 -o $@ -p $^ + +$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc + icepack $^ $@ + +%.rpt: $(BUILDDIR)/%.asc + icetime -d $(DEVICE) -mtr $@ $< + +%_tb.vvp: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb.vvp + vvp -N $< +vcd=$@ + +# ------ APPLE 1 ------ +apple1: dir $(BUILDDIR)/apple1.bin +report: dir apple1.rpt + +$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc +$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif +$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \ + $(SOURCEDIR)/clock.v \ + $(SOURCEDIR)/pwr_reset.v \ + $(SOURCEDIR)/ram.v \ + $(SOURCEDIR)/rom_wozmon.v \ + $(SOURCEDIR)/rom_basic.v \ + $(SOURCEDIR)/cpu/arlet_6502.v \ + $(SOURCEDIR)/cpu/arlet/ALU.v \ + $(SOURCEDIR)/cpu/arlet/cpu.v \ + $(SOURCEDIR)/uart/uart.v \ + $(SOURCEDIR)/uart/async_tx_rx.v \ + $(SOURCEDIR)/vga/vga.v \ + $(SOURCEDIR)/vga/vram.v \ + $(SOURCEDIR)/vga/font_rom.v \ + $(SOURCEDIR)/ps2keyboard/debounce.v \ + $(SOURCEDIR)/ps2keyboard/ps2keyboard.v \ + clock_pll.v \ + apple1_hx8k.v + +apple1.rpt: $(BUILDDIR)/apple1.asc + +prog: dir $(BUILDDIR)/apple1.bin + tinyfpgab -p $(filter-out $<,$^) + +# ------ HELPERS ------ +clean: + rm -rf build apple1.rpt + +.SECONDARY: +.PHONY: all info clean prog iceprog diff --git a/boards/tinyfpga_yosys/apple1_hx8k.v b/boards/tinyfpga_yosys/apple1_hx8k.v new file mode 100644 index 0000000..051bca0 --- /dev/null +++ b/boards/tinyfpga_yosys/apple1_hx8k.v @@ -0,0 +1,92 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: Apple 1 implementation for the iCE40HX8K dev +// board. +// +// Author.....: Miodrag Milanovic +// Date.......: 11-2-2018 +// + +module apple1_top( + input pin3_clk_16mhz,// 16 MHz board clock + + // Outputs to VGA display + output pin4, // hozizontal VGA sync pulse + output pin5, // vertical VGA sync pulse + + input pin6, // PS/2 data input + input pin7, // PS/2 clock + + // I/O interface to computer + input pin11, // asynchronous serial data input from computer + output pin12, // asynchronous serial data output to computer + output pin13, // clear to send flag to computer + + output reg pin24, // red VGA signal + output reg pin23, // red VGA signal + output reg pin22, // green VGA signal + output reg pin21, // green VGA signal + output reg pin20, // blue VGA signal + output reg pin19 // blue VGA signal + +); + + wire clk25; + + // 16MHz up to 25MHz + clock_pll clock_pll_inst( + .REFERENCECLK(pin3_clk_16mhz), + .PLLOUTGLOBAL(clk25), + .RESET(1'b1) + ); + + wire [15:0] pc_monitor; + + reg [1:0] button = 2'b01; + + wire vga_red; + wire vga_grn; + wire vga_blu; + + // apple one main system + apple1 my_apple1( + .clk25(clk25), + .rst_n(button[0]), + .ps2_clk(pin7), + .ps2_din(pin6), + .ps2_select(1'b0), + .uart_rx(pin11), + .uart_tx(pin12), + .uart_cts(pin13), + .clr_screen_btn(button[1]), + .vga_h_sync(pin4), + .vga_v_sync(pin5), + .vga_red(vga_red), + .vga_grn(vga_grn), + .vga_blu(vga_blu), + .pc_monitor(pc_monitor) + ); + + assign pin19 = vga_blu; + assign pin20 = vga_blu; + assign pin21 = vga_grn; + assign pin22 = vga_grn; + assign pin23 = vga_red; + assign pin24 = vga_red; + +endmodule diff --git a/boards/tinyfpga_yosys/clock_pll.v b/boards/tinyfpga_yosys/clock_pll.v new file mode 100644 index 0000000..879fe5d --- /dev/null +++ b/boards/tinyfpga_yosys/clock_pll.v @@ -0,0 +1,38 @@ +module clock_pll(REFERENCECLK, + PLLOUTCORE, + PLLOUTGLOBAL, + RESET); + +input REFERENCECLK; +input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ +output PLLOUTCORE; +output PLLOUTGLOBAL; + +SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK), + .PLLOUTCORE(PLLOUTCORE), + .PLLOUTGLOBAL(PLLOUTGLOBAL), + .EXTFEEDBACK(), + .DYNAMICDELAY(), + .RESETB(RESET), + .BYPASS(1'b0), + .LATCHINPUTVALUE(), + .LOCK(), + .SDI(), + .SDO(), + .SCLK()); + +//\\ Fin=16, Fout=25; +defparam clock_pll_inst.DIVR = 4'b0000; +defparam clock_pll_inst.DIVF = 7'b0110001; +defparam clock_pll_inst.DIVQ = 3'b101; +defparam clock_pll_inst.FILTER_RANGE = 3'b001; +defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE"; +defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; +defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000; +defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; +defparam clock_pll_inst.FDA_RELATIVE = 4'b0000; +defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00; +defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK"; +defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0; + +endmodule diff --git a/boards/tinyfpga_yosys/tinyfpga.pcf b/boards/tinyfpga_yosys/tinyfpga.pcf new file mode 100644 index 0000000..fc5ab03 --- /dev/null +++ b/boards/tinyfpga_yosys/tinyfpga.pcf @@ -0,0 +1,29 @@ +# For the TinyFPGA Computer Project Board + +### left side of board +#set_io --warn-no-port pin1_usb_dp A3 +#set_io --warn-no-port pin2_usb_dn A4 +set_io --warn-no-port pin3_clk_16mhz B4 +set_io --warn-no-port pin4 B2 +set_io --warn-no-port pin5 A2 +set_io --warn-no-port pin6 A1 +set_io --warn-no-port pin7 B1 +#set_io --warn-no-port pin8 C1 +#set_io --warn-no-port pin9 D1 +#set_io --warn-no-port pin10 E1 +set_io --warn-no-port pin11 G1 +set_io --warn-no-port pin12 H1 +set_io --warn-no-port pin13 J1 + +### right side of board +#set_io --warn-no-port pin14_sdo G6 +#set_io --warn-no-port pin15_sdi H7 +#set_io --warn-no-port pin16_sck G7 +#set_io --warn-no-port pin17_ss F7 +#set_io --warn-no-port pin18 D9 +set_io --warn-no-port pin19 C9 +set_io --warn-no-port pin20 E8 +set_io --warn-no-port pin21 A9 +set_io --warn-no-port pin22 A8 +set_io --warn-no-port pin23 A7 +set_io --warn-no-port pin24 A6 \ No newline at end of file