Apple-1-HW/verilog-apple-one
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Fixed issue with basic ROM

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This commit is contained in:
Alan Garfield 2018-01-12 01:01:34 +11:00
parent 158510c299
commit 697bd34798
4 changed files with 569 additions and 4170 deletions
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5
.gitignore vendored
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@ -1,4 +1,7 @@
*_Implmnt
*.xcf
*.log
synlog.tcl
synlog.tcl
*~
*.bak
*.swp

6
apple1_sbt.project
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@ -4,7 +4,7 @@ Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Bui
ProjectName=apple1
Vendor=SiliconBlue
Synthesis=synplify
ProjectVFiles=basic.v=work,uart.v=work,tm1638.v=work,led_and_key.v=work,chip_6502.v,MUX.v
ProjectVFiles=basic.v=work,uart.v=work,tm1638.v=work,led_and_key.v=work,chip_6502.v=work,MUX.v=work
ProjectCFiles=
CurImplementation=apple1_Implmnt
Implementations=apple1_Implmnt
@ -16,11 +16,11 @@ DeviceFamily=iCE40
Device=HX8K
DevicePackage=CT256
DevicePower=
NetlistFile=
NetlistFile=apple1_Implmnt/apple1.edf
AdditionalEDIFFile=
IPEDIFFile=
DesignLib=apple1_Implmnt/sbt/netlist/oadb-top
DesignView=
DesignView=_rt
DesignCell=top
SynthesisSDCFile=apple1_Implmnt/apple1.scf
UserPinConstraintFile=

4608
basic.hex
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File diff suppressed because it is too large Load Diff

120
basic.v
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@ -16,67 +16,18 @@ module top(
output reg [7:0] led
);
wire clk_phi;
wire res, rw, irq, nmi;
wire [15:0] ab;
wire [7:0] dbo;
reg [7:0] dbi;
//////////////////////////////////////////////////////////////////////////
// CLK DIVIDER
/*
wire clk;
clk_div u_clk_div(
.clk (clk12),
.clk_out (clk)
);
*/
//////////////////////////////////////////////////////////////////////////
// 6502 reset
reg [7:0] start;
always @(posedge clk)
if (~start[7]) start <= start + 1;
assign res = start[7];
//////////////////////////////////////////////////////////////////////////
// 6502 phi0 clock
reg [3:0] div;
always @(posedge clk)
div <= div + 1;
wire clk_phi;
SB_GB bg_phi (
.USER_SIGNAL_TO_GLOBAL_BUFFER(div[3]),
.GLOBAL_BUFFER_OUTPUT(clk_phi)
);
//////////////////////////////////////////////////////////////////////////
// 6502
chip_6502 chip_6502 (
.clk (clk),
.phi (clk_phi),
.res (res),
.so (1'b0),
.rdy (1'b1),
.nmi (nmi),
.irq (irq),
.rw (rw),
.dbi (dbi),
.dbo (dbo),
.sync (),
.ab (ab)
);
//////////////////////////////////////////////////////////////////////////
// USB UART
wire received, is_receiving, rx_error, is_transmitting, transmit;
reg [6:0] tx_byte;
wire [7:0] rx_byte;
wire received, is_receiving, rx_error, is_transmitting, transmit;
reg [6:0] tx_byte;
wire [7:0] rx_byte;
uart #(.CLOCK_DIVIDE( 625 )) my_uart (
clk, // master clock for this component
@ -94,14 +45,6 @@ module top(
// sync the TX latch to the clk domain
reg apple_tx;
/*
Flag_CrossDomain tx_flag (
.clkA(clk_phi),
.FlagIn_clkA(apple_tx),
.clkB(clk),
.FlagOut_clkB(transmit)
);
*/
assign transmit = apple_tx;
// sync the RX flag, using flag and ack
@ -152,29 +95,66 @@ module top(
);
`endif
//////////////////////////////////////////////////////////////////////////
// 6502 reset
reg [7:0] start;
always @(posedge clk)
if (~start[7]) start <= start + 1;
assign res = start[7];
//////////////////////////////////////////////////////////////////////////
// 6502 phi0 clock
reg [3:0] div;
always @(posedge clk)
div <= div + 1;
SB_GB bg_phi (
.USER_SIGNAL_TO_GLOBAL_BUFFER(div[3]),
.GLOBAL_BUFFER_OUTPUT(clk_phi)
);
//////////////////////////////////////////////////////////////////////////
// 6502
chip_6502 chip_6502 (
.clk (clk),
.phi (clk_phi),
.res (res && ~keys[0]),
.so (1'b0),
.rdy (1'b1),
.nmi (nmi),
.irq (irq),
.rw (rw),
.dbi (dbi),
.dbo (dbo),
.ab (ab)
);
//////////////////////////////////////////////////////////////////////////
// I/O locations
localparam UART_RX = 16'hD010; // PIA.A register on Apple 1 - RX byte
localparam UART_RXCR = 16'hD011; // PIA.A register on Apple 1 - RX control
localparam UART_TX = 16'hD012; // PIA.B register on Apple 1 - TX byte
localparam LED_KEYS = 16'hD020; // Start address of the Led&Keys module
localparam LED = 16'hD000; // Breakout board LEDs
localparam UART_RX = 16'hD010; // PIA.A register on Apple 1 - RX byte
localparam UART_RXCR = 16'hD011; // PIA.A register on Apple 1 - RX control
localparam UART_TX = 16'hD012; // PIA.B register on Apple 1 - TX byte
localparam LED_KEYS = 16'hD020; // Start address of the Led&Keys module
localparam LED = 16'hD000; // Breakout board LEDs
//////////////////////////////////////////////////////////////////////////
// RAM and ROM
reg [7:0] ram[0:8191] /* synthesis syn_ramstyle = "block_ram" */;
reg [7:0] basic[0:4091] /* synthesis syn_ramstyle = "block_ram" */;
reg [7:0] rom[0:255] /* synthesis syn_ramstyle = "block_ram" */;
reg [7:0] basic[0:4095] /* synthesis syn_ramstyle = "block_ram" */;
initial begin
$readmemh("../ram.hex", ram, 0, 8191);
$readmemh("../rom.hex", rom, 0, 255);
$readmemh("../basic.hex", basic, 0, 4091);
$readmemh("../basic.hex", basic, 0, 4095);
end
//always @(posedge clk_phi)
always @(posedge clk_phi)
begin
// clear the UART RX ack if set
@ -259,7 +239,7 @@ module top(
end
else
// unknown address return zero
dbi <= 8'b0;
dbi <= 8'h0;
end
endcase