mirror of
https://github.com/alangarf/apple-one.git
synced 2024-06-06 01:29:27 +00:00
added basic rom and fix uart issue on HX
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164cb06992
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@ -4,7 +4,7 @@ Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Bui
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ProjectName=appleone
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Vendor=SiliconBlue
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Synthesis=synplify
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ProjectVFiles=../../rtl/rom_wozmon.v=work,../../rtl/apple1.v=work,../../rtl/ram.v=work,../../rtl/boards/ice40hx8k/clock_pll.v=work,../../rtl/uart/async_tx_rx.v=work,../../rtl/uart/uart.v=work,../../rtl/boards/ice40hx8k/apple1_hx8k.v=work,../../rtl/cpu/arlet_6502.v=work,../../rtl/cpu/arlet/ALU.v=work,../../rtl/cpu/arlet/cpu.v=work
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ProjectVFiles=../../rtl/rom_wozmon.v=work,../../rtl/apple1.v=work,../../rtl/ram.v=work,../../rtl/boards/ice40hx8k/clock_pll.v=work,../../rtl/uart/async_tx_rx.v=work,../../rtl/uart/uart.v=work,../../rtl/boards/ice40hx8k/apple1_hx8k.v=work,../../rtl/cpu/arlet_6502.v=work,../../rtl/cpu/arlet/ALU.v=work,../../rtl/cpu/arlet/cpu.v=work,../../rtl/rom_basic.v
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ProjectCFiles=appleone_syn.sdc
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CurImplementation=appleone_Implmnt
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Implementations=appleone_Implmnt
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@ -19,9 +19,9 @@ DevicePower=
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NetlistFile=appleone_Implmnt/appleone.edf
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AdditionalEDIFFile=
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IPEDIFFile=
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DesignLib=
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DesignView=
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DesignCell=
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DesignLib=appleone_Implmnt/sbt/netlist/oadb-apple1_top
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DesignView=_rt
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DesignCell=apple1_top
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SynthesisSDCFile=appleone_Implmnt/appleone.scf
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UserPinConstraintFile=
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UserSDCFile=
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@ -18,6 +18,7 @@ add_file -verilog -lib work "../../rtl/boards/ice40hx8k/apple1_hx8k.v"
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add_file -verilog -lib work "../../rtl/cpu/arlet_6502.v"
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add_file -verilog -lib work "../../rtl/cpu/arlet/ALU.v"
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add_file -verilog -lib work "../../rtl/cpu/arlet/cpu.v"
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add_file -verilog -lib work "../../rtl/rom_basic.v"
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add_file -constraint -lib work "appleone_syn.sdc"
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#implementation: "appleone_Implmnt"
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impl -add appleone_Implmnt -type fpga
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@ -9,12 +9,7 @@ set_io uart_tx B12
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set_io uart_cts A15
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#set_io uart_rts B13
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### TM1638 Display
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#set_io tm_clk P1
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#set_io tm_dio P2
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#set_io tm_cs R1
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### LEDs
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### Breakout Board LEDs
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set_io led[7] B5
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set_io led[6] B4
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set_io led[5] A2
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@ -24,25 +19,23 @@ set_io led[2] C4
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set_io led[1] B3
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set_io led[0] C3
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set_io ledx[7] J1
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set_io ledx[6] J2
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set_io ledx[5] K1
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set_io ledx[4] K3
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set_io ledx[3] L1
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set_io ledx[2] L3
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set_io ledx[1] M1
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set_io ledx[0] M2
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### YL-4 Switch Matrix LEDs (inverted)
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set_io led[15] J1
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set_io led[14] J2
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set_io led[13] K1
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set_io led[12] K3
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set_io led[11] L1
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set_io led[10] L3
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set_io led[9] M1
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set_io led[8] M2
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#set_io d[0] B1
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#set_io d[1] B2
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#set_io d[2] C1
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#set_io d[3] C2
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#set_io d[4] D1
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#set_io d[5] D2
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#set_io d[6] E2
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#set_io d[7] F1
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#set_io d[8] F2
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#set_io d[9] G1
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#set_io d[10] G2
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#set_io d[11] H1
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#set_io d[12] H2
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### YL-4 Switch Marix Buttons
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set_io button[3] E2
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set_io button[2] F1
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set_io button[1] F2
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set_io button[0] G1
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### TM1638 Display
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#set_io tm_clk P1
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#set_io tm_dio P2
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#set_io tm_cs R1
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@ -5,5 +5,6 @@
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../rtl/uart/uart.v
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../rtl/ram.v
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../rtl/rom_wozmon.v
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../rtl/rom_basic.v
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../rtl/apple1.v
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apple1_tb.v
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@ -216,7 +216,8 @@ module apple1_tb;
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// Core of system
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apple1 #(
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"../roms/ram.hex",
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"../roms/wozmon.hex"
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"../roms/wozmon.hex",
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"../roms/basic.hex"
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) core_top (
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.clk25(clk25),
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.rst_n(rst_n),
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36
rtl/apple1.v
36
rtl/apple1.v
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@ -5,11 +5,12 @@ module apple1(
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input uart_rx,
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output uart_tx,
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output uart_cts,
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output [15:0] pc_monitor // spy for program counter / debugging
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);
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parameter RAM_FILENAME = "../../roms/ram.hex";
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parameter WOZ_FILENAME = "../../roms/wozmon.hex";
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parameter BASIC_FILENAME = "../../roms/basic.hex";
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//////////////////////////////////////////////////////////////////////////
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// Registers and Wires
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@ -18,11 +19,11 @@ module apple1(
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wire [7:0] dbi;
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wire [7:0] dbo;
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wire we;
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//////////////////////////////////////////////////////////////////////////
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// Clocks
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// generate clock enable once every
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// generate clock enable once every
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// 25 clocks. This will (hopefully) make
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// the 6502 run at 1 MHz or 1Hz
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//
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@ -45,7 +46,7 @@ module apple1(
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clk_div <= clk_div + 1'b1;
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cpu_clken <= (clk_div[25:0] == 0);
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end
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end
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`else
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reg [4:0] clk_div;
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reg cpu_clken;
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@ -115,7 +116,6 @@ module apple1(
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wire [7:0] ram_dout;
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ram #(RAM_FILENAME) my_ram (
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.clk(clk25),
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.reset(reset),
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.address(ab[12:0]),
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.w_en(we & ram_cs),
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.din(dbo),
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@ -126,19 +126,26 @@ module apple1(
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wire [7:0] rom_dout;
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rom_wozmon #(WOZ_FILENAME) my_rom_wozmon (
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.clk(clk25),
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.reset(reset),
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.address(ab[7:0]),
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.dout(rom_dout)
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);
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// Basic ROM
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wire [7:0] basic_dout;
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rom_basic #(BASIC_FILENAME) my_rom_basic (
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.clk(clk25),
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.address(ab[7:0]),
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.dout(basic_dout)
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);
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// UART
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wire [7:0] uart_dout;
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uart #(
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`ifdef SIM
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100, 10, 2 // for simulation don't need real baud rates
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`else
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25000000, 115200, 8
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// FIXME:
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// If simulated, need to reduce baud rate etc down
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// else the UARTs don't work.
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// 100, 10, 2
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`endif
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)my_uart (
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.clk(clk25),
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.reset(reset),
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@ -155,8 +162,9 @@ module apple1(
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);
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// link up chip selected device to cpu input
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assign dbi = ram_cs ? ram_dout :
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rom_cs ? rom_dout :
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uart_cs ? uart_dout :
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assign dbi = ram_cs ? ram_dout :
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rom_cs ? rom_dout :
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basic_cs ? basic_dout :
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uart_cs ? uart_dout :
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8'hFF;
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endmodule
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@ -3,7 +3,9 @@ module apple1_top(
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input uart_rx,
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output uart_tx,
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output uart_cts
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output uart_cts,
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output [15:0] led,
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output [1:0] button
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);
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wire clk25;
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.RESET(1'b1)
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);
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wire [15:0] pc_monitor;
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assign led[7:0] = pc_monitor[7:0];
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assign led[15:8] = ~pc_monitor[15:8];
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// apple one main system
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apple1 my_apple1(
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.clk25(clk25),
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.rst_n(1'b1),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts)
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.uart_cts(uart_cts),
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.pc_monitor(pc_monitor)
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);
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endmodule
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@ -1,6 +1,5 @@
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module ram(
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input clk,
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input reset,
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input [12:0] address,
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input w_en,
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input [7:0] din,
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@ -16,8 +15,8 @@ module ram(
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always @(posedge clk)
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begin
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dout <= reset ? 8'h0 : ram[address];
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if (w_en && ~reset) ram[address] <= din;
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dout <= ram[address];
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if (w_en) ram[address] <= din;
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end
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endmodule
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17
rtl/rom_basic.v
Normal file
17
rtl/rom_basic.v
Normal file
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@ -0,0 +1,17 @@
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module rom_basic(
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input clk,
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input [7:0] address,
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output reg [7:0] dout
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);
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parameter ROM_FILENAME = "../roms/basic.hex";
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reg [7:0] rom[0:4095];
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initial
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$readmemh(ROM_FILENAME, rom, 0, 4095);
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always @(posedge clk)
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dout <= rom[address];
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endmodule
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@ -1,6 +1,5 @@
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module rom_wozmon(
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input clk,
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input reset,
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input [7:0] address,
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output reg [7:0] dout
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);
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$readmemh(ROM_FILENAME, rom, 0, 255);
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always @(posedge clk)
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begin
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dout <= reset ? 8'h0 : rom[address];
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end
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dout <= rom[address];
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endmodule
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@ -108,13 +108,18 @@ module uart(
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begin
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// Apple 1 terminal only uses 7 bits, MSB indicates
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// terminal has ack'd RX
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//
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// uart_tx_init is a flag to stop the first character
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// sent to the UART from being sent. Wozmon initializes
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// the PIA which normally isn't sent to the terminal.
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// This causes the UART to ignore the very first byte sent.
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if (~uart_tx_status && uart_tx_init)
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begin
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uart_tx_byte <= {1'b0, din[6:0]};
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uart_tx_stb <= 1;
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end
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else
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uart_tx_init <= 1;
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else if (~uart_tx_init)
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uart_tx_init <= 1 && enable;
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end
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end
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