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![Apple One](https://github.com/alangarf/apple-one/raw/master/media/apple-logo.png)
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![Apple One](media/apple-logo.png)
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This is a basic implementation of the original Apple 1 in Verilog for an iCE40HX FPGA. It can run the Apple 1 WozMon and Integer Basic via the serial USB interface which is available on the iCE40HX8K-B-EVN breakout board. This makes this a very compact little set up. There is no reason this cannot be implemented for other FPGAs with very little work.
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![iCE40HX8K](https://github.com/alangarf/apple-one/raw/master/media/iCE40HX8K-breakout.png)
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![iCE40HX8K](boards/ice40hx9k-b-evn/images/iCE40HX8K-breakout.png)
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This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project where he built a 6502 CPU core in Verilog using the netlist from the Visual 6502 project. Amazing stuff, and so far seems to work perfectly. Also many special thanks to ["sbprojects.com"](https://www.sbprojects.com/projects/apple1/index.php) for the wealth of information I gleaned from there.
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Maintainer: Alan Garfield https://github.com/alangarf
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![iCE40HX8K board photo](https://github.com/alangarf/apple-one/raw/master/media/iCE40HX8K-breakout.png)
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![iCE40HX8K board photo](images/iCE40HX8K-breakout.png)
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### Build environment
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The project was started with IceCube2, and the project files are in the subdirectory 'icecube2'. These haven't been updated in a while, but should prove a worthy starting point. I'll endeavour to keep them updated when I can.
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Before Width: | Height: | Size: 39 KiB After Width: | Height: | Size: 39 KiB |
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