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## Constraints for Nexys 3 Board
## - Oskar Andrzej Stepien
## -- April 2019
##
## Clock signal
NET "CLK_100MHZ" LOC = V10 | IOSTANDARD = "LVCMOS33"; #Bank = 2, pin name = IO_L30N_GCLK0_USERCCLK, Sch name = GCLK
##
## 7 segment display
NET "SEG<0>" LOC = T17 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = CA
NET "SEG<1>" LOC = T18 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L51N_M1DQ13, Sch name = CB
NET "SEG<2>" LOC = U17 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L52P_M1DQ14, Sch name = CC
NET "SEG<3>" LOC = U18 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = CD
NET "SEG<4>" LOC = M14 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L53P, Sch name = CE
NET "SEG<5>" LOC = N14 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L53N_VREF, Sch name = CF
NET "SEG<6>" LOC = L14 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L61P, Sch name = CG
NET "DP" LOC = M13 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L61N, Sch name = DP
NET "AN<0>" LOC = N16 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L50N_M1UDQSN, Sch name = AN0
NET "AN<1>" LOC = N15 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L50P_M1UDQS, Sch name = AN1
NET "AN<2>" LOC = P18 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L49N_M1DQ11, Sch name = AN2
NET "AN<3>" LOC = P17 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L49P_M1DQ10, Sch name = AN3
##
## Leds
NET "LED_KB" LOC = U16 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = LD0
#NET "Led<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = LD1
NET "LED_MEMSEL<0>" LOC = U15 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5P, Sch name = LD2
NET "LED_MEMSEL<1>" LOC = V15 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5N, Sch name = LD3
#NET "Led<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15P, Sch name = LD4
#NET "Led<5>" LOC = N11 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15N, Sch name = LD5
NET "LED_LOADING" LOC = R11 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16P, Sch name = LD6
NET "LED_INIT" LOC = T11 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16N_VREF, Sch name = LD7
##
## Switches
NET "SWITCH" LOC = T10 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L29N_GCLK2, Sch name = SW0
#NET "sw<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32P_GCLK29, Sch name = SW1
NET "MEMSEL<0>" LOC = V9 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32N_GCLK28, Sch name = SW2
NET "MEMSEL<1>" LOC = M8 | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L40P, Sch name = SW3
#NET "sw<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L40N, Sch name = SW4
#NET "sw<5>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L41P, Sch name = SW5
#NET "sw<6>" LOC = "V8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L41N_VREF, Sch name = SW6
#NET "sw<7>" LOC = "T5" | IOSTANDARD = "LVCMOS33"; #Bank = MISC, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7
##
## Buttons
Net "BTN_OK" LOC = B8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33P, Sch name = BTNS
Net "BUTTON" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33N, Sch name = BTNU
Net "BTN_PREV" LOC = C4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L1N_VREF, Sch name = BTNL
Net "VGA_CLR" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L34N_GCLK18, Sch name = BTND
Net "BTN_NEXT" LOC = D9 | IOSTANDARD = LVCMOS33; # Bank = 0, pin name = IO_L34P_GCLK19, Sch name = BTNR Sch name = BTNR
##
## VGA Connector
#NET "VGA_R<0>" LOC = U7 | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L43P, Sch name = RED0
#NET "VGA_R<1>" LOC = "V7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L43N, Sch name = RED1
NET "VGA_R" LOC = N7 | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L44P, Sch name = RED2
#NET "VGA_G<0>" LOC = P8 | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L44N, Sch name = GRN0
#NET "VGA_G<1>" LOC = "T6" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L45P, Sch name = GRN1
NET "VGA_G" LOC = V6 | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L45N, Sch name = GRN2
#NET "VGA_B<1>" LOC = R7 | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L46P, Sch name = BLU1
NET "VGA_B" LOC = T7 | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L46N, Sch name = BLU2
NET "VGA_HS" LOC = N6 | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L47P, Sch name = HSYNC
NET "VGA_VS" LOC = P7 | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L47N, Sch name = VSYNC
##
## Pic USB-HID interface
NET "PS2_KBDAT" LOC = J13 | IOSTANDARD = "LVCMOS33" | PULLUP; #Bank = 1, Pin name = IO_L39P_M1A3, Sch name = PIC-SDI1
NET "PS2_KBCLK" LOC = L12 | IOSTANDARD = "LVCMOS33" | PULLUP; #Bank = 1, Pin name = IO_L40P_GCLK11_M1A5, Sch name = PIC-SCK1
#NET "PS2MouseData" LOC = "K14" | IOSTANDARD = "LVCMOS33" | PULLUP; #Bank = 1, Pin name = IO_L39N_M1ODT, Sch name = PIC-SDO1
#NET "PS2MouseClk" LOC = "L13" | IOSTANDARD = "LVCMOS33" | PULLUP; #Bank = 1, Pin name = IO_L40N_GCLK10_M1A6, Sch name = PIC-SS1
#NET "PicGpio<0>" LOC = "L16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = PIC-GPIO0
#NET "PicGpio<1>" LOC = "H17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L43P_GCLK5_M1DQ4, Sch name = PIC-GPIO1
##
## Usb-RS232 interface
NET "UART_RXD" LOC = N17 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX
NET "UART_TXD" LOC = N18 | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L48N_M1DQ9, Sch name = MCU-TX
##
#Created by Constraints Editor (xc6slx16-csg324-2) - 2019/03/04
NET "CLK_100MHZ" TNM_NET = CLK_100MHZ;
TIMESPEC TS_CLOCK_100MHZ = PERIOD "CLK_100MHZ" 10 ns HIGH 50%;
NET "clk25" TNM_NET = clk25;
TIMESPEC TS_CLOCK_25MHZ = PERIOD "clk25" 40 ns HIGH 50%;

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441
boards/spartan6_nexys3/webpack/apple_one_nexys3.xise Normal file
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@ -0,0 +1,441 @@
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<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
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</project>