diff --git a/boards/spartan3e_starterkit/webpack_ise/Apple-One.gise b/boards/spartan3e_starterkit/webpack_ise/Apple-One.gise
index 19662ab..ee21b02 100644
--- a/boards/spartan3e_starterkit/webpack_ise/Apple-One.gise
+++ b/boards/spartan3e_starterkit/webpack_ise/Apple-One.gise
@@ -103,7 +103,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1518446552" xil_pn:in_ck="-2402892782883100176" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8720043281624233679" xil_pn:start_ts="1518446533">
+    <transform xil_pn:end_ts="1518447977" xil_pn:in_ck="-2402892782883100176" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8720043281624233679" xil_pn:start_ts="1518447958">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -125,7 +125,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1518446557" xil_pn:in_ck="-3894786652928293112" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-581701490373080307" xil_pn:start_ts="1518446552">
+    <transform xil_pn:end_ts="1518447982" xil_pn:in_ck="-3894786652928293112" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-581701490373080307" xil_pn:start_ts="1518447977">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_ngo"/>
@@ -134,11 +134,9 @@
       <outfile xil_pn:name="apple1_s3e_starterkit_top.ngd"/>
       <outfile xil_pn:name="apple1_s3e_starterkit_top_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1518446561" xil_pn:in_ck="8375880660293788329" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1518446557">
+    <transform xil_pn:end_ts="1518447986" xil_pn:in_ck="8375880660293788329" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1518447982">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
       <outfile xil_pn:name="apple1_s3e_starterkit_top.pcf"/>
       <outfile xil_pn:name="apple1_s3e_starterkit_top_map.map"/>
@@ -149,7 +147,7 @@
       <outfile xil_pn:name="apple1_s3e_starterkit_top_summary.xml"/>
       <outfile xil_pn:name="apple1_s3e_starterkit_top_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1518446578" xil_pn:in_ck="-3296291810439397278" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1518446561">
+    <transform xil_pn:end_ts="1518448003" xil_pn:in_ck="-3296291810439397278" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1518447986">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@@ -163,7 +161,7 @@
       <outfile xil_pn:name="apple1_s3e_starterkit_top_pad.txt"/>
       <outfile xil_pn:name="apple1_s3e_starterkit_top_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1518446588" xil_pn:in_ck="-5976217886481471090" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1518446578">
+    <transform xil_pn:end_ts="1518448066" xil_pn:in_ck="-5976217886481471090" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1518448055">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -178,8 +176,10 @@
     <transform xil_pn:end_ts="1518446623" xil_pn:in_ck="-5976217886481483944" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1518446622">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputChanged"/>
     </transform>
-    <transform xil_pn:end_ts="1518446578" xil_pn:in_ck="-6485470272289971291" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518446575">
+    <transform xil_pn:end_ts="1518448003" xil_pn:in_ck="-6485470272289971291" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518447999">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
diff --git a/roms/wozmon.hex b/roms/wozmon.hex
index f3bd6d1..70a749c 100644
--- a/roms/wozmon.hex
+++ b/roms/wozmon.hex
@@ -1,32 +1,256 @@
-D8 58 A0 7F 8C 12 D0 A9
-A7 8D 11 D0 8D 13 D0 C9
-DF F0 13 C9 9B F0 03 C8
-10 0F A9 DC 20 EF FF A9
-8D 20 EF FF A0 01 88 30
-F6 AD 11 D0 10 FB AD 10
-D0 99 00 02 20 EF FF C9
-8D D0 D4 A0 FF A9 00 AA
-0A 85 2B C8 B9 00 02 C9
-8D F0 D4 C9 AE 90 F4 F0
-F0 C9 BA F0 EB C9 D2 F0
-3B 86 28 86 29 84 2A B9
-00 02 49 B0 C9 0A 90 06
-69 88 C9 FA 90 11 0A 0A
-0A 0A A2 04 0A 26 28 26
-29 CA D0 F8 C8 D0 E0 C4
-2A F0 97 24 2B 50 10 A5
-28 81 26 E6 26 D0 B5 E6
-27 4C 44 FF 6C 24 00 30
-2B A2 02 B5 27 95 25 95
-23 CA D0 F7 D0 14 A9 8D
-20 EF FF A5 25 20 DC FF
-A5 24 20 DC FF A9 BA 20
-EF FF A9 A0 20 EF FF A1
-24 20 DC FF 86 2B A5 24
-C5 28 A5 25 E5 29 B0 C1
-E6 24 D0 02 E6 25 A5 24
-29 07 10 C8 48 4A 4A 4A
-4A 20 E5 FF 68 29 0F 09
-B0 C9 BA 90 02 69 06 2C
-12 D0 30 FB 8D 12 D0 60
-00 00 00 0F 00 FF 00 00
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\ No newline at end of file
diff --git a/rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v b/rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v
new file mode 100644
index 0000000..7b34def
--- /dev/null
+++ b/rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v
@@ -0,0 +1,90 @@
+// Licensed to the Apache Software Foundation (ASF) under one
+// or more contributor license agreements.  See the NOTICE file
+// distributed with this work for additional information
+// regarding copyright ownership.  The ASF licenses this file
+// to you under the Apache License, Version 2.0 (the
+// "License"); you may not use this file except in compliance
+// with the License.  You may obtain a copy of the License at
+//
+//   http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// software distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+// Description: Top level Apple 1 module for Digilent Spartan 3E
+//              starter kit board
+//
+// Author.....: Niels A. Moseley
+// Date.......: 11-2-2018
+// 
+
+
+module apple1_s3e_starterkit_top #(
+    parameter BASIC_FILENAME      = "../../../roms/basic_ise.hex",
+    parameter FONT_ROM_FILENAME   = "../../../roms/vga_font_bitreversed.hex",
+    parameter RAM_FILENAME        = "../../../roms/ram_ise.hex",
+    parameter VRAM_FILENAME       = "../../../roms/vga_vram.bin",
+    parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon_ise.hex"
+) (    
+    input   CLK_50MHZ,      // the 50 MHz master clock
+
+    // UART I/O signals
+    output  UART_TXD,       // UART transmit pin on board
+    input   UART_RXD,       // UART receive pin on board
+        
+    input   PS2_KBCLK,
+    input   PS2_KBDAT,
+
+    input   BUTTON,
+
+    output  VGA_R,
+    output  VGA_G,
+    output  VGA_B,
+    output  VGA_HS,
+    output  VGA_VS    
+);
+
+    //////////////////////////////////////////////////////////////////////////    
+    // Registers and Wires
+    reg clk25;
+    wire [15:0] pc_monitor;
+
+    wire rst_n;    
+    assign rst_n = ~BUTTON;
+
+    // generate 25MHz clock from 50MHz master clock
+    always @(posedge CLK_50MHZ)
+    begin
+        clk25 <= ~clk25;
+    end    
+    
+    //////////////////////////////////////////////////////////////////////////    
+    // Core of system
+    apple1 #(
+        .BASIC_FILENAME (BASIC_FILENAME),
+        .FONT_ROM_FILENAME (FONT_ROM_FILENAME),
+        .RAM_FILENAME (RAM_FILENAME),
+        .VRAM_FILENAME (VRAM_FILENAME),
+        .WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
+    ) apple1_top(
+        .clk25(clk25),
+        .rst_n(rst_n),         // we don't have any reset pulse..
+        .uart_rx(UART_RXD),
+        .uart_tx(UART_TXD),
+        //.uart_cts(UART_CTS),  // there is no CTS on the board :(
+        .ps2_clk(PS2_KBCLK),
+        .ps2_din(PS2_KBDAT),
+        .ps2_select(1'b1),
+        .vga_h_sync(VGA_HS),
+        .vga_v_sync(VGA_VS),
+        .vga_red(VGA_R),
+        .vga_grn(VGA_G),
+        .vga_blu(VGA_B),
+        .pc_monitor(pc_monitor)
+    );
+    
+endmodule