From 7b3c65b8d9fa2af05ab0ef83d57a8bfd6e8c20f0 Mon Sep 17 00:00:00 2001
From: Alan Garfield <alan@fromorbit.com>
Date: Mon, 5 Feb 2018 00:24:12 +1100
Subject: [PATCH] Fixed issue with yosys compile

---
 boards/ice40hx8k_yosys/Makefile |  1 +
 rtl/apple1.v                    |  8 +++-----
 rtl/vga/vga.v                   |  1 -
 rtl/vga/vram.v                  | 14 +++-----------
 4 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/boards/ice40hx8k_yosys/Makefile b/boards/ice40hx8k_yosys/Makefile
index 078cbae..71c8c34 100644
--- a/boards/ice40hx8k_yosys/Makefile
+++ b/boards/ice40hx8k_yosys/Makefile
@@ -53,6 +53,7 @@ $(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
 	$(SOURCEDIR)/uart/async_tx_rx.v \
 	$(SOURCEDIR)/vga/vga.v \
 	$(SOURCEDIR)/vga/vram.v \
+	$(SOURCEDIR)/vga/font_rom.v \
 	$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
 	$(SOURCEDIR)/boards/ice40hx8k/clock_pll.v \
 	$(SOURCEDIR)/boards/ice40hx8k/apple1_hx8k.v
diff --git a/rtl/apple1.v b/rtl/apple1.v
index 3876fc6..af3023b 100644
--- a/rtl/apple1.v
+++ b/rtl/apple1.v
@@ -90,8 +90,8 @@ module apple1(
         .we     (we),
         .irq_n  (1'b1),
         .nmi_n  (1'b1),
-        .ready  (cpu_clken)
-        //.pc_monitor (pc_monitor)
+        .ready  (cpu_clken),
+        .pc_monitor (pc_monitor)
     );
 
     //////////////////////////////////////////////////////////////////////////
@@ -198,9 +198,7 @@ module apple1(
         .w_en(we & vga_cs),
         .din(dbo),
 
-        .clr_screen_btn(clr_screen_btn),
-        .blink_clken(blink_clken),
-        .debug(pc_monitor)
+        .blink_clken(blink_clken)
     );
 
     //////////////////////////////////////////////////////////////////////////
diff --git a/rtl/vga/vga.v b/rtl/vga/vga.v
index 992ec7d..68f3e09 100644
--- a/rtl/vga/vga.v
+++ b/rtl/vga/vga.v
@@ -114,7 +114,6 @@ module vga(
 
     vram my_vram(
         .clk(clk25),
-        .rst(rst),
         .read_addr(vram_r_addr),
         .write_addr(vram_w_addr),
         .r_en(h_active),
diff --git a/rtl/vga/vram.v b/rtl/vga/vram.v
index ab653e8..cdf1706 100644
--- a/rtl/vga/vram.v
+++ b/rtl/vga/vram.v
@@ -24,7 +24,6 @@
 
 module vram(
     input clk,                  // clock signal
-    input rst,                  //
     input [9:0] read_addr,      // read address bus
     input [9:0] write_addr,     // write address bus
     input r_en,                 // active high read enable strobe
@@ -44,17 +43,10 @@ module vram(
     initial
         $readmemb(RAM_FILENAME, ram_data, 0, 1023);
 
-    always @(posedge clk or posedge rst )
+    always @(posedge clk)
     begin
-        if (rst)
-            dout <= 0;
-        else
-        begin
-            //if (r_en) dout <= ram_data[read_addr];
-            dout <= ram_data[read_addr];
-            if (w_en) ram_data[write_addr] <= din;
-        end
+        if (r_en) dout <= ram_data[read_addr];
+        if (w_en) ram_data[write_addr] <= din;
     end
 
 endmodule
-