From 99fc3e6ef55913b1e0afb3b7a37f0266d19076f0 Mon Sep 17 00:00:00 2001 From: Alan Garfield Date: Sun, 21 Oct 2018 21:06:21 +1100 Subject: [PATCH] added initial test of tinyfpga bx --- boards/tinyfpga_bx/tinyfpga_bx.pcf | 17 ++++ boards/tinyfpga_bx/yosys/Makefile | 82 +++++++++++++++++ boards/tinyfpga_bx/yosys/tinyfpga_bx.pcf | 1 + rtl/boards/tinyfpga_bx/apple1_hx8k.v | 107 +++++++++++++++++++++++ rtl/boards/tinyfpga_bx/clock_pll.v | 38 ++++++++ 5 files changed, 245 insertions(+) create mode 100644 boards/tinyfpga_bx/tinyfpga_bx.pcf create mode 100644 boards/tinyfpga_bx/yosys/Makefile create mode 120000 boards/tinyfpga_bx/yosys/tinyfpga_bx.pcf create mode 100644 rtl/boards/tinyfpga_bx/apple1_hx8k.v create mode 100644 rtl/boards/tinyfpga_bx/clock_pll.v diff --git a/boards/tinyfpga_bx/tinyfpga_bx.pcf b/boards/tinyfpga_bx/tinyfpga_bx.pcf new file mode 100644 index 0000000..9126c10 --- /dev/null +++ b/boards/tinyfpga_bx/tinyfpga_bx.pcf @@ -0,0 +1,17 @@ +## System Clock +set_io clk B2 + +## VGA Display +set_io vga_red A6 +set_io vga_grn B6 +set_io vga_blu A7 +set_io vga_h_sync B7 +set_io vga_v_sync A8 + +## UART +set_io uart_tx B1 +set_io uart_rx C2 + +## Lighthouse +set_io lt_dat H1 +set_io lt_env J1 diff --git a/boards/tinyfpga_bx/yosys/Makefile b/boards/tinyfpga_bx/yosys/Makefile new file mode 100644 index 0000000..83b3fa4 --- /dev/null +++ b/boards/tinyfpga_bx/yosys/Makefile @@ -0,0 +1,82 @@ +DEVICE = 8k +PACKAGE = cm81 +FREQ_OSC = 16 +FREQ_PLL = 25 + +PIN_DEF=tinyfpga_bx.pcf + +SOURCEDIR = ../../../rtl +BUILDDIR = build + +PLL = $(BUILDDIR)/pll.sv + +all: apple1 prog + +info: + @echo " To build: make apple1" + @echo " To program: make prog" + @echo "To build report: make report" + @echo " To clean up: make clean" + +dir: + mkdir -p $(BUILDDIR) + +# ------ TEMPLATES ------ +$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v + yosys -q -p "synth_ice40 -top apple1_top -blif $@" $^ + +$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif + arachne-pnr -d $(DEVICE) -P $(PACKAGE) -o $@ -p $^ + +$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc + icepack $^ $@ + +%.rpt: $(BUILDDIR)/%.asc + icetime -d $(DEVICE) -mtr $@ $< + +%_tb.vvp: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb.vvp + vvp -N $< +vcd=$@ + +$(PLL): + icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@ + +# ------ APPLE 1 ------ +apple1: dir $(BUILDDIR)/apple1.bin +report: dir apple1.rpt + +$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc +$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif +$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \ + $(SOURCEDIR)/clock.v \ + $(SOURCEDIR)/pwr_reset.v \ + $(SOURCEDIR)/ram.v \ + $(SOURCEDIR)/rom_wozmon.v \ + $(SOURCEDIR)/rom_basic.v \ + $(SOURCEDIR)/cpu/arlet_6502.v \ + $(SOURCEDIR)/cpu/arlet/ALU.v \ + $(SOURCEDIR)/cpu/arlet/cpu.v \ + $(SOURCEDIR)/uart/uart.v \ + $(SOURCEDIR)/uart/async_tx_rx.v \ + $(SOURCEDIR)/vga/vga.v \ + $(SOURCEDIR)/vga/vram.v \ + $(SOURCEDIR)/vga/font_rom.v \ + $(SOURCEDIR)/ps2keyboard/debounce.v \ + $(SOURCEDIR)/ps2keyboard/ps2keyboard.v \ + $(SOURCEDIR)/boards/tinyfpga_bx/clock_pll.v \ + $(SOURCEDIR)/boards/tinyfpga_bx/apple1_hx8k.v \ + $(BUILDDIR)/pll.sv + +apple1.rpt: $(BUILDDIR)/apple1.asc + +prog: dir $(BUILDDIR)/apple1.bin + tinyprog -p $(filter-out $<,$^) + +# ------ HELPERS ------ +clean: + rm -rf build apple1.rpt + +.SECONDARY: +.PHONY: all info clean prog iceprog diff --git a/boards/tinyfpga_bx/yosys/tinyfpga_bx.pcf b/boards/tinyfpga_bx/yosys/tinyfpga_bx.pcf new file mode 120000 index 0000000..4f5deaf --- /dev/null +++ b/boards/tinyfpga_bx/yosys/tinyfpga_bx.pcf @@ -0,0 +1 @@ +../tinyfpga_bx.pcf \ No newline at end of file diff --git a/rtl/boards/tinyfpga_bx/apple1_hx8k.v b/rtl/boards/tinyfpga_bx/apple1_hx8k.v new file mode 100644 index 0000000..70ec654 --- /dev/null +++ b/rtl/boards/tinyfpga_bx/apple1_hx8k.v @@ -0,0 +1,107 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: Apple 1 implementation for the iCE40HX8K dev +// board. +// +// Author.....: Miodrag Milanovic +// Date.......: 11-2-2018 +// + +module apple1_top #( + parameter BASIC_FILENAME = "../../../roms/basic.hex", + parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex", + parameter RAM_FILENAME = "../../../roms/ram.hex", + parameter VRAM_FILENAME = "../../../roms/vga_vram.bin", + parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex" +) ( + input clk, // 16 MHz board clock + + // I/O interface to computer + input uart_rx, // asynchronous serial data input from computer + output uart_tx, // asynchronous serial data output to computer + + // Outputs to VGA display + output vga_h_sync, // hozizontal VGA sync pulse + output vga_v_sync, // vertical VGA sync pulse + output reg vga_red, // red VGA signal + output reg vga_grn, // green VGA signal + output reg vga_blu, // blue VGA signal + + inout lt_dat, + inout lt_env +); + + wire clk25; + + // 16MHz up to 25MHz + clock_pll clock_pll_inst( + .REFERENCECLK(clk), + .PLLOUTGLOBAL(clk25), + .RESET(1'b1) + ); + + reg lt_data_rw; + wire lt_data_in, lt_data_out; + SB_IO #( + .PIN_TYPE(6'b101001), + .PULLUP(1'b1) + ) lt_dat_io ( + .PACKAGE_PIN(lt_dat), + .OUTPUT_ENABLE(lt_data_rw), + .D_IN_0(lt_data_in), + .D_OUT_0(lt_data_out) + ); + + reg lt_env_rw; + wire lt_env_in, lt_env_out; + SB_IO #( + .PIN_TYPE(6'b101001), + .PULLUP(1'b1) + ) lt_env_io ( + .PACKAGE_PIN(lt_env), + .OUTPUT_ENABLE(lt_env_rw), + .D_IN_0(lt_env_in), + .D_OUT_0(lt_env_out) + ); + + + // apple one main system + apple1 #( + .BASIC_FILENAME (BASIC_FILENAME), + .FONT_ROM_FILENAME (FONT_ROM_FILENAME), + .RAM_FILENAME (RAM_FILENAME), + .VRAM_FILENAME (VRAM_FILENAME), + .WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME) + ) my_apple1( + .clk25(clk25), + .rst_n(1'b1), + //.ps2_clk(), + //.ps2_din(), + .ps2_select(1'b1), + .uart_rx(uart_tx), + .uart_tx(uart_rx), + //.uart_cts(), + .vga_h_sync(vga_h_sync), + .vga_v_sync(vga_v_sync), + .vga_red(vga_red), + .vga_grn(vga_grn), + .vga_blu(vga_blu) + //.pc_monitor(pc_monitor) + ); + +endmodule diff --git a/rtl/boards/tinyfpga_bx/clock_pll.v b/rtl/boards/tinyfpga_bx/clock_pll.v new file mode 100644 index 0000000..879fe5d --- /dev/null +++ b/rtl/boards/tinyfpga_bx/clock_pll.v @@ -0,0 +1,38 @@ +module clock_pll(REFERENCECLK, + PLLOUTCORE, + PLLOUTGLOBAL, + RESET); + +input REFERENCECLK; +input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ +output PLLOUTCORE; +output PLLOUTGLOBAL; + +SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK), + .PLLOUTCORE(PLLOUTCORE), + .PLLOUTGLOBAL(PLLOUTGLOBAL), + .EXTFEEDBACK(), + .DYNAMICDELAY(), + .RESETB(RESET), + .BYPASS(1'b0), + .LATCHINPUTVALUE(), + .LOCK(), + .SDI(), + .SDO(), + .SCLK()); + +//\\ Fin=16, Fout=25; +defparam clock_pll_inst.DIVR = 4'b0000; +defparam clock_pll_inst.DIVF = 7'b0110001; +defparam clock_pll_inst.DIVQ = 3'b101; +defparam clock_pll_inst.FILTER_RANGE = 3'b001; +defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE"; +defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; +defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000; +defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; +defparam clock_pll_inst.FDA_RELATIVE = 4'b0000; +defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00; +defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK"; +defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0; + +endmodule