Apple-1-HW/verilog-apple-one
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Fixed DE0 compilation problems

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This commit is contained in:
Niels Moseley 2018-02-19 00:29:30 +01:00
parent 8066942b40
commit a0dae6f9a7
2 changed files with 2 additions and 2 deletions
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2
rtl/apple1.v
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@ -201,7 +201,7 @@ module apple1 #(
reg [2:0] fg_colour;
reg [2:0] bg_colour;
reg [1:0] font_mode;
wire [7:0] vga_mode_dout;
reg [7:0] vga_mode_dout;
vga #(
.VRAM_FILENAME (VRAM_FILENAME),

2
rtl/vga/vram.v
View File

@ -23,7 +23,7 @@
//
module vram #(
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin"
) (
input clk, // clock signal
input [10:0] read_addr, // read address bus