diff --git a/boards/tinyfpga_bx/icecube2/icecube2_sbt.project b/boards/tinyfpga_bx/icecube2/icecube2_sbt.project
new file mode 100644
index 0000000..2ec3d81
--- /dev/null
+++ b/boards/tinyfpga_bx/icecube2/icecube2_sbt.project
@@ -0,0 +1,88 @@
+[Project]
+ProjectVersion=2.0
+Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Build Date: Sep 11 2017 17:40:01
+ProjectName=icecube2
+Vendor=SiliconBlue
+Synthesis=synplify
+ProjectVFiles=../../../../rtl/apple1.v,../../../../rtl/clock.v,../../../../rtl/pwr_reset.v,../../../../rtl/ram.v,../../../../rtl/rom_basic.v,../../../../rtl/rom_wozmon.v,../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v,../../../../rtl/boards/tinyfpga_bx/clock_pll.v,../../../../rtl/cpu/arlet_6502.v,../../../../rtl/cpu/arlet/ALU.v,../../../../rtl/cpu/arlet/cpu.v,../../../../rtl/ps2keyboard/debounce.v,../../../../rtl/ps2keyboard/ps2keyboard.v,../../../../rtl/uart/async_tx_rx.v,../../../../rtl/uart/uart.v,../../../../rtl/vga/font_rom.v,../../../../rtl/vga/vga.v,../../../../rtl/vga/vram.v
+ProjectCFiles=
+CurImplementation=icecube2_Implmnt
+Implementations=icecube2_Implmnt
+StartFromSynthesis=yes
+IPGeneration=false
+
+[icecube2_Implmnt]
+DeviceFamily=iCE40
+Device=LP8K
+DevicePackage=CM81
+DevicePower=
+NetlistFile=icecube2_Implmnt/icecube2.edf
+AdditionalEDIFFile=
+IPEDIFFile=
+DesignLib=icecube2_Implmnt/sbt/netlist/oadb-apple1_top
+DesignView=_rt
+DesignCell=apple1_top
+SynthesisSDCFile=icecube2_Implmnt/icecube2.scf
+UserPinConstraintFile=
+UserSDCFile=
+PhysicalConstraintFile=../tinyfpga_bx.pcf
+BackendImplPathName=
+Devicevoltage=1.14
+DevicevoltagePerformance=+/-5%(datasheet default)
+DeviceTemperature=85
+TimingAnalysisBasedOn=Worst
+OperationRange=Commercial
+TypicalCustomTemperature=25
+WorstCustomTemperature=85
+BestCustomTemperature=0
+IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3
+derValue=1.03369
+TimingPathNumberStick=0
+
+[lse options]
+CarryChain=True
+CarryChainLength=0
+CommandLineOptions=
+EBRUtilization=100.00
+FSMEncodingStyle=Auto
+FixGatedClocks=True
+I/OInsertion=True
+IntermediateFileDump=False
+LoopLimit=1950
+MaximalFanout=10000
+MemoryInitialValueFileSearchPath=
+NumberOfCriticalPaths=3
+OptimizationGoal=Area
+PropagateConstants=True
+RAMStyle=Auto
+ROMStyle=Auto
+RWCheckOnRam=False
+RemoveDuplicateRegisters=True
+ResolvedMixedDrivers=False
+ResourceSharing=True
+TargetFrequency=
+TopLevelUnit=
+UseIORegister=Auto
+VHDL2008=False
+VerilogIncludeSearchPath=
+
+[tool options]
+PlacerEffortLevel=std
+PlacerAutoLutCascade=yes
+PlacerAutoRamCascade=yes
+PlacerPowerDriven=no
+PlacerAreaDriven=no
+RouteWithTimingDriven=yes
+RouteWithPinPermutation=yes
+BitmapSPIFlashMode=yes
+BitmapRAM4KInit=yes
+BitmapInitRamBank=1111
+BitmapOscillatorFR=low
+BitmapEnableWarmBoot=yes
+BitmapDisableHeader=no
+BitmapSetSecurity=no
+BitmapSetNoUsedIONoPullup=no
+FloorPlannerShowFanInNets=yes
+FloorPlannerShowFanOutNets=yes
+HookTo3rdPartyTextEditor=
+
diff --git a/boards/tinyfpga_bx/icecube2/icecube2_syn.prj b/boards/tinyfpga_bx/icecube2/icecube2_syn.prj
new file mode 100644
index 0000000..84b4bf9
--- /dev/null
+++ b/boards/tinyfpga_bx/icecube2/icecube2_syn.prj
@@ -0,0 +1,73 @@
+#-- Synopsys, Inc.
+#-- Project file Z:\boards\tinyfpga_bx\\icecube2\icecube2_syn.prj
+#project files
+add_file -verilog -lib work "../../../../rtl/apple1.v"
+add_file -verilog -lib work "../../../../rtl/clock.v"
+add_file -verilog -lib work "../../../../rtl/pwr_reset.v"
+add_file -verilog -lib work "../../../../rtl/ram.v"
+add_file -verilog -lib work "../../../../rtl/rom_basic.v"
+add_file -verilog -lib work "../../../../rtl/rom_wozmon.v"
+add_file -verilog -lib work "../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v"
+add_file -verilog -lib work "../../../../rtl/boards/tinyfpga_bx/clock_pll.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet_6502.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet/ALU.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet/cpu.v"
+add_file -verilog -lib work "../../../../rtl/ps2keyboard/debounce.v"
+add_file -verilog -lib work "../../../../rtl/ps2keyboard/ps2keyboard.v"
+add_file -verilog -lib work "../../../../rtl/uart/async_tx_rx.v"
+add_file -verilog -lib work "../../../../rtl/uart/uart.v"
+add_file -verilog -lib work "../../../../rtl/vga/font_rom.v"
+add_file -verilog -lib work "../../../../rtl/vga/vga.v"
+add_file -verilog -lib work "../../../../rtl/vga/vram.v"
+
+#implementation: "icecube2_Implmnt"
+impl -add icecube2_Implmnt -type fpga
+
+#implementation attributes
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#device options
+set_option -technology SBTiCE40
+set_option -part iCE40LP8K
+set_option -package CM81
+set_option -speed_grade 
+set_option -part_companion ""
+
+#compilation/mapping options
+
+# mapper_options
+set_option -frequency auto
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Silicon Blue iCE40
+set_option -maxfan 10000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -retiming 0
+set_option -update_models_cp 0
+set_option -fixgatedclocks 2
+set_option -fixgeneratedclocks 0
+
+# NFilter
+set_option -popfeed 0
+set_option -constprop 0
+set_option -createhierarchy 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file ./icecube2_Implmnt/icecube2.edf
+project -log_file "./icecube2_Implmnt/icecube2.srr"
+impl -active "icecube2_Implmnt"
+project -run synthesis -clean
diff --git a/rtl/apple1.v b/rtl/apple1.v
index 44e535e..5b9fca1 100644
--- a/rtl/apple1.v
+++ b/rtl/apple1.v
@@ -177,7 +177,7 @@ module apple1 #(
         .uart_rx(uart_rx),
         .uart_tx(uart_tx),
 
-        .address(ab[1:0]),        // for uart
+        .address(ab[1:0]),
         .w_en(we & uart_cs),
         .din(dbo),
         .dout(uart_dout)
diff --git a/rtl/boards/tinyfpga_bx/apple1_hx8k.v b/rtl/boards/tinyfpga_bx/apple1_hx8k.v
index 550676d..935d024 100644
--- a/rtl/boards/tinyfpga_bx/apple1_hx8k.v
+++ b/rtl/boards/tinyfpga_bx/apple1_hx8k.v
@@ -56,7 +56,7 @@ module apple1_top #(
             );
 
     // lighthouse sensor
-    reg lt_data_rw;
+    wire lt_data_rw;
     wire lt_data_in, lt_data_out;
     SB_IO #(
         .PIN_TYPE(6'b101001),
@@ -68,7 +68,7 @@ module apple1_top #(
         .D_OUT_0(lt_data_out)
     );
 
-    reg lt_env_rw;
+    wire lt_env_rw;
     wire lt_env_in, lt_env_out;
     SB_IO #(
         .PIN_TYPE(6'b101001),
@@ -98,12 +98,11 @@ module apple1_top #(
     ) my_apple1(
         .clk25(clk25),
         .rst_n(1'b1),
-        .ps2_select(1'b0),
         .uart_rx(uart_rx),
         .uart_tx(uart_tx),
         .ps2_clk(1'b0),
         .ps2_din(1'b0),
-        .ps2_select(1'b0),
+        .ps2_select(1'b1),
         .vga_h_sync(vga_h_sync),
         .vga_v_sync(vga_v_sync),
         .vga_red(vga_red),
diff --git a/rtl/boards/tinyfpga_bx/clock_pll.v b/rtl/boards/tinyfpga_bx/clock_pll.v
index 879fe5d..f13f233 100644
--- a/rtl/boards/tinyfpga_bx/clock_pll.v
+++ b/rtl/boards/tinyfpga_bx/clock_pll.v
@@ -11,15 +11,15 @@ output PLLOUTGLOBAL;
 SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
                              .PLLOUTCORE(PLLOUTCORE),
                              .PLLOUTGLOBAL(PLLOUTGLOBAL),
-                             .EXTFEEDBACK(),
-                             .DYNAMICDELAY(),
+                             .EXTFEEDBACK(1'd0),
+                             .DYNAMICDELAY(8'd0),
                              .RESETB(RESET),
                              .BYPASS(1'b0),
-                             .LATCHINPUTVALUE(),
+                             .LATCHINPUTVALUE(1'd0),
                              .LOCK(),
-                             .SDI(),
+                             .SDI(1'd0),
                              .SDO(),
-                             .SCLK());
+                             .SCLK(1'd0));
 
 //\\ Fin=16, Fout=25;
 defparam clock_pll_inst.DIVR = 4'b0000;