From b2ebc23e3af8467f238d2b6adcfb7fcceb4ee97a Mon Sep 17 00:00:00 2001 From: Alan Garfield Date: Mon, 29 Jan 2018 22:15:21 +1100 Subject: [PATCH] added license headers and tidied up --- boards/ice40hx8k/ice40hx8k.pcf | 16 +++++------ boards/ice40hx8k_yosys/Makefile | 6 ++-- rtl/apple1.v | 2 +- rtl/boards/ice40hx8k/apple1_hx8k.v | 41 ++++++++++++++++++++++---- rtl/clock.v | 2 +- rtl/cpu/arlet_6502.v | 46 +++++++++++++++++++++++------- rtl/pwr_reset.v | 33 ++++++++++++++++++--- rtl/ram.v | 34 ++++++++++++++++++---- rtl/rom_basic.v | 30 +++++++++++++++++-- rtl/rom_wozmon.v | 30 +++++++++++++++++-- rtl/uart/uart.v | 43 +++++++++++++++++++--------- 11 files changed, 226 insertions(+), 57 deletions(-) diff --git a/boards/ice40hx8k/ice40hx8k.pcf b/boards/ice40hx8k/ice40hx8k.pcf index 8a95350..8af8e08 100644 --- a/boards/ice40hx8k/ice40hx8k.pcf +++ b/boards/ice40hx8k/ice40hx8k.pcf @@ -20,14 +20,14 @@ set_io led[1] B3 set_io led[0] C3 ### YL-4 Switch Matrix LEDs (inverted) -set_io led[15] J1 -set_io led[14] J2 -set_io led[13] K1 -set_io led[12] K3 -set_io led[11] L1 -set_io led[10] L3 -set_io led[9] M1 -set_io led[8] M2 +set_io ledx[7] J1 +set_io ledx[6] J2 +set_io ledx[5] K1 +set_io ledx[4] K3 +set_io ledx[3] L1 +set_io ledx[2] L3 +set_io ledx[1] M1 +set_io ledx[0] M2 ### YL-4 Switch Marix Buttons set_io button[3] E2 diff --git a/boards/ice40hx8k_yosys/Makefile b/boards/ice40hx8k_yosys/Makefile index 6b3cc7a..bbb22a6 100644 --- a/boards/ice40hx8k_yosys/Makefile +++ b/boards/ice40hx8k_yosys/Makefile @@ -4,7 +4,9 @@ PIN_DEF=ice40hx8k.pcf SOURCEDIR = ../../rtl BUILDDIR = build -all: +all: apple1 prog + +info: @echo " To build: make apple1" @echo " To program: make prog" @echo "To build report: make report" @@ -63,4 +65,4 @@ clean: rm -rf build apple1.rpt .SECONDARY: -.PHONY: all clean prog iceprog +.PHONY: all info clean prog iceprog diff --git a/rtl/apple1.v b/rtl/apple1.v index d4f3e9a..75de670 100644 --- a/rtl/apple1.v +++ b/rtl/apple1.v @@ -137,13 +137,13 @@ module apple1( `endif ) my_uart( .clk(clk25), + .enable(uart_cs & cpu_clken), .rst(rst), .uart_rx(uart_rx), .uart_tx(uart_tx), .uart_cts(uart_cts), - .enable(uart_cs & cpu_clken), //.address({1'b1, ab[0]}), // for ps/2 .address(ab[1:0]), .w_en(we & uart_cs), diff --git a/rtl/boards/ice40hx8k/apple1_hx8k.v b/rtl/boards/ice40hx8k/apple1_hx8k.v index 1c89fb5..f83c594 100644 --- a/rtl/boards/ice40hx8k/apple1_hx8k.v +++ b/rtl/boards/ice40hx8k/apple1_hx8k.v @@ -1,11 +1,40 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: Apple 1 implementation for the iCE40HX8K dev +// board. +// +// Author.....: Alan Garfield +// Date.......: 26-1-2018 +// + module apple1_top( input clk, // 12 MHz board clock - input uart_rx, - output uart_tx, - output uart_cts, - output [15:0] led, - input [3:0] button + // I/O interface to computer + input uart_rx, // asynchronous serial data input from computer + output uart_tx, // asynchronous serial data output to computer + output uart_cts, // clear to send flag to computer + + // Debugging ports + output [7:0] led, // 8 LEDs on the iCE40HX8K board + + output [7:0] ledx, // 8 LEDs on optionally attached YL-4 board + input [3:0] button // 4 buttons on optionall attached YL-4 board ); wire clk25; @@ -19,7 +48,7 @@ module apple1_top( wire [15:0] pc_monitor; assign led[7:0] = pc_monitor[7:0]; - assign led[15:8] = ~pc_monitor[15:8]; + assign ledx[7:0] = ~pc_monitor[15:8]; // TODO: debounce buttons diff --git a/rtl/clock.v b/rtl/clock.v index 6edd30e..2098365 100644 --- a/rtl/clock.v +++ b/rtl/clock.v @@ -24,7 +24,7 @@ // module clock( - input clk25, // 25MHz clock + input clk25, // 25MHz clock master clock input rst_n, // active low synchronous reset // Clock enables diff --git a/rtl/cpu/arlet_6502.v b/rtl/cpu/arlet_6502.v index ea98d71..7ea97d5 100644 --- a/rtl/cpu/arlet_6502.v +++ b/rtl/cpu/arlet_6502.v @@ -1,14 +1,38 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: A wrapper for Arlet Ottens 6502 CPU core +// +// Author.....: Alan Garfield +// Niels A. Moseley +// Date.......: 26-1-2018 +// + module arlet_6502( - input clk, // clock signal - input enable, // clock enable strobe - input rst, // active high reset signal - output reg [15:0] ab, // address bus - input [7:0] dbi, // 8-bit data bus (input) - output reg [7:0] dbo, // 8-bit data bus (output) - output reg we, // active high write enable strobe - input irq_n, // active low interrupt request - input nmi_n, // active low non-maskable interrupt - input ready, // CPU updates when ready = 1 + input clk, // clock signal + input enable, // clock enable strobe + input rst, // active high reset signal + output reg [15:0] ab, // address bus + input [7:0] dbi, // 8-bit data bus (input) + output reg [7:0] dbo, // 8-bit data bus (output) + output reg we, // active high write enable strobe + input irq_n, // active low interrupt request + input nmi_n, // active low non-maskable interrupt + input ready, // CPU updates when ready = 1 output [15:0] pc_monitor // program counter monitor signal for debugging ); @@ -16,7 +40,7 @@ module arlet_6502( wire [15:0] ab_c; wire we_c; - cpu arlet_cpu ( + cpu arlet_cpu( .clk(clk), .reset(rst), .AB(ab_c), diff --git a/rtl/pwr_reset.v b/rtl/pwr_reset.v index bae2226..8140f73 100644 --- a/rtl/pwr_reset.v +++ b/rtl/pwr_reset.v @@ -1,8 +1,33 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: Clock divider to provide clock enables for +// devices. +// +// Author.....: Alan Garfield +// Niels A. Moseley +// Date.......: 29-1-2018 +// + module pwr_reset( - input clk25, - input rst_n, - input enable, - output rst + input clk25, // 25Mhz master clock + input rst_n, // active low synchronous reset + input enable, // clock enable + output rst // active high synchronous system reset ); reg hard_reset; diff --git a/rtl/ram.v b/rtl/ram.v index be6b46f..f999e93 100644 --- a/rtl/ram.v +++ b/rtl/ram.v @@ -1,9 +1,33 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: 8KB RAM for system +// +// Author.....: Alan Garfield +// Niels A. Moseley +// Date.......: 26-1-2018 +// + module ram( - input clk, - input [12:0] address, - input w_en, - input [7:0] din, - output reg [7:0] dout + input clk, // clock signal + input [12:0] address, // address bus + input w_en, // active high write enable strobe + input [7:0] din, // 8-bit data bus (input) + output reg [7:0] dout // 8-bit data bus (output) ); `ifdef SIM diff --git a/rtl/rom_basic.v b/rtl/rom_basic.v index b271e62..4179432 100644 --- a/rtl/rom_basic.v +++ b/rtl/rom_basic.v @@ -1,7 +1,31 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: Wrapper for Apple Integer Basic ROM +// +// Author.....: Alan Garfield +// Niels A. Moseley +// Date.......: 26-1-2018 +// + module rom_basic( - input clk, - input [11:0] address, - output reg [7:0] dout + input clk, // clock signal + input [11:0] address, // address bus + output reg [7:0] dout // 8-bit data bus (output) ); `ifdef SIM diff --git a/rtl/rom_wozmon.v b/rtl/rom_wozmon.v index 48e70fc..660cabe 100644 --- a/rtl/rom_wozmon.v +++ b/rtl/rom_wozmon.v @@ -1,7 +1,31 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: Wrapper for the Woz Mon ROM +// +// Author.....: Alan Garfield +// Niels A. Moseley +// Date.......: 26-1-2018 +// + module rom_wozmon( - input clk, - input [7:0] address, - output reg [7:0] dout + input clk, // clock signal + input [7:0] address, // address bus + output reg [7:0] dout // 8-bit data bus (output) ); `ifdef SIM diff --git a/rtl/uart/uart.v b/rtl/uart/uart.v index bf43da0..59016a3 100644 --- a/rtl/uart/uart.v +++ b/rtl/uart/uart.v @@ -1,22 +1,39 @@ +// Licensed to the Apache Software Foundation (ASF) under one +// or more contributor license agreements. See the NOTICE file +// distributed with this work for additional information +// regarding copyright ownership. The ASF licenses this file +// to you under the Apache License, Version 2.0 (the +// "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at // -// Just add the .v file to the project +// http://www.apache.org/licenses/LICENSE-2.0 // +// Unless required by applicable law or agreed to in writing, +// software distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +// +// Description: A wrapper for the basic UART from fpga4fun.com +// +// Author.....: Alan Garfield +// Niels A. Moseley +// Date.......: 26-1-2018 // -//`include "./async_tx_rx.v" module uart( - input clk, - input rst, + input clk, // clock signal + input enable, // clock enable strobe + input rst, // active high reset signal + input [1:0] address, // address bus + input w_en, // active high write enable strobe + input [7:0] din, // 8-bit data bus (input) + output reg [7:0] dout, // 8-bit data bus (output) - input enable, - input [1:0] address, - input w_en, - input [7:0] din, - output reg [7:0] dout, - - input uart_rx, - output uart_tx, - output uart_cts + input uart_rx, // asynchronous serial data input from computer + output uart_tx, // asynchronous serial data output to computer + output uart_cts // clear to send flag to computer ); parameter ClkFrequency = 25000000; // 25MHz