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# apple-one
![Apple One](https://github.com/alangarf/apple-one/raw/master/media/apple-logo.png)
This is a very untested and very basic implementation of an Apple 1 in a iCE40HX FPGA. It has enough to run Woz Mon via the serial USB interface which is available on the iCE40HX8K-B-EVN breakout board, which makes this a very compact little set up.
This is a basic implementation of the original Apple 1 in Verilog for an iCE40HX FPGA. It can run the Apple 1 WozMon and Integer Basic via the serial USB interface which is available on the iCE40HX8K-B-EVN breakout board. This makes this a very compact little set up. There is no reason this cannot be implemented for other FPGAs with very little work.
I've also wired up support for a LED&KEYS IO board using my TM1638 verilog module.
This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project where he built a 6502 CPU core in Verilog using the netlist from the Visual 6502 project. Amazing stuff, and so far seems to work perfectly. Also many thanks to many thanks to ["sbprojects.com"](https://www.sbprojects.com/projects/apple1/index.php) for the wealth of information there.
This project borrows heavily from the work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project where he built a 6502 CPU core in Verilog using the netlist from the Visual 6502 project. Amazing stuff, and so far seems to work perfectly.
As it stands this project uses the following resources in the iCE40HX8K
```
Total Logic Cells: 1739/7680
 Combinational Logic Cells: 634 out of 7680 (8.25%)
 Sequential Logic Cells:   1105 out of 7680 (14.38%)
 Logic Tiles:               295 out of 960 (30.72%)
Registers:
 Logic Registers:           1105 out of 7680 (14.38%)
 IO Registers:             0     out of 1280 (0%)
Block RAMS:                 16 out of 32 (50%)
Global Buffers:             6     out of 8 (75%)
PLLs:                       0     out of 2 (0%)
```
## Memory Map
The memory is as basic as basic can be. 50% of the iCE40HX8K is used currently, but this gives the Apple 1 basically 8K of memory which is plenty to start with.
The Zero page and Stack page is covered, and a small 256 byte "ROM" is positioned up at 0xFF00 -> 0xFFFF.
The iCE40HX8K has 16KB of available block RAM, this is currently set up to have:
- 8KB of system RAM (0x0000 -> 0x1FFF)
- 4KB of Integer Basic ROM (0xE000 -> 0xEFFF)
- 512B of WozMON ROM (0xFF00 -> 0xFFFF)
The remaining 3.5KB is being earmarked for character ROMs and video RAM when I start implementing that (any help greatfully accepted). The basic ROM could be removed which would allow for 12KB of system RAM if needs be.
Start | End | Description
----- | --- | -----------
0x0000 | 0x1FFF | 8KB of block RAM. 0x1F00 -> 0x1FFF is the "ROM" data.
0xD000 | | Output register for the breakout LEDs
0xD010 | | UART RX register used by Woz Mon
0xD011 || UART RX control register. Woz Mon checks the MSB for received flag
0xD012 | | UART TX register and control. The TX register only writes 7 bits to the remote host. The MSB is read by Woz Mon to confirm the UART isn't busy sending
0xD020 | | LED&KEYs display register. [4] is display on/off, [3:0] is brightness
0xD021|0xD028| LED&KEYs digit data for digit 1 to 8
0xD029 | | LED&KEYs LEDs 1 to 8
0xD030 | | LED&KEys input register for the buttons 1 to 8. [7] is button 1, [0] is button 8
0xFF00 | 0xFFFF | Woz Mon pointed to by the RESET vector
0x0000 | 0x1FFF | 8KB of block RAM for system
0xE000 | 0xEFFF | 4KB of block RAM for basic ROM
0xFF00 | 0xFFFF | 512B of block RAM for WozMon ROM
## Hardware Map
I've implemented a few physical hardware peripherals in this design, and also added a UART inplace of the PIA used in the original Apple 1, this allows USB communucation with the system very similar to the "terminal" in the original.
I've also added support for the commonly available TM1638 based LED&KEY board. This allows 8 x 7 segment displays, 8 x LEDs and 8 x push buttons all in an easily addressable way.
Start | End | Description
----- | --- | -----------
0xD000 | | Output register for the eight LEDs on the breakout board
0xD010 | | UART RX register
0xD011 | | UART RX control register
0xD012 | | UART TX register and control
0xD020 | | LED&KEY display register. [4] is display on/off, [3:0] is brightness
0xD021 | 0xD028 | LED&KEY digit data for digit 1 to 8
0xD029 | | LED&KEY LEDs 1 to 8
0xD030 | | LED&KEY input register for the buttons 1 to 8. [7] is button 1, [0] is button 8
## Building
This project should just build with IceCube2 without any issue, and I will figure out how to make it work with Yosys shortly.
At the moment yosys/arachne-pr fails to properly synth the project, mostly due to the complexity of the gate-level logic implementation of the 6502.
## External Devices / Hook-up
To connect the LED&KEYs to the breakout board the following pins are defined in the constraints file.
To connect the LED&KEY to the breakout board the following pins are defined in the constraints file.
Pin | ID | Description
--- | -- | -----------