Yay got iverilog sim working!

iverilog/apple1_tb.v

@@ -32,20 +32,156 @@ module apple1_tb;
     // Setup dumping of data for inspection
 
     initial begin
-        force core_top.my_cpu.arlet_cpu.DIHOLD = 0;
+        force core_top.clk_div = 0;
-        force core_top.my_cpu.arlet_cpu.ALU.OUT = 0;
+        force core_top.cpu_clken = 0;
+        force core_top.hard_reset = 0;
+        force core_top.reset_cnt = 0;
+
+        force core_top.my_cpu.arlet_cpu.AB = 0;
         force core_top.my_cpu.arlet_cpu.PC = 0;
+        force core_top.my_cpu.arlet_cpu.ABL = 0;
+        force core_top.my_cpu.arlet_cpu.ABH = 0;
+        force core_top.my_cpu.arlet_cpu.DIHOLD = 0;
+        force core_top.my_cpu.arlet_cpu.IRHOLD = 0;
+        force core_top.my_cpu.arlet_cpu.IRHOLD_valid = 0;
+        force core_top.my_cpu.arlet_cpu.C = 0;
+        force core_top.my_cpu.arlet_cpu.Z = 0;
+        force core_top.my_cpu.arlet_cpu.I = 0;
+        force core_top.my_cpu.arlet_cpu.D = 0;
+        force core_top.my_cpu.arlet_cpu.V = 0;
+        force core_top.my_cpu.arlet_cpu.N = 0;
+        force core_top.my_cpu.arlet_cpu.AI = 0;
+        force core_top.my_cpu.arlet_cpu.BI = 0;
+        force core_top.my_cpu.arlet_cpu.DO = 0;
+        force core_top.my_cpu.arlet_cpu.WE = 0;
+        force core_top.my_cpu.arlet_cpu.CI = 0;
+        force core_top.my_cpu.arlet_cpu.NMI_edge = 0;
+        force core_top.my_cpu.arlet_cpu.regsel = 0;
+        force core_top.my_cpu.arlet_cpu.PC_inc = 0;
+        force core_top.my_cpu.arlet_cpu.PC_temp = 0;
+        force core_top.my_cpu.arlet_cpu.src_reg = 0;
+        force core_top.my_cpu.arlet_cpu.dst_reg = 0;
+        force core_top.my_cpu.arlet_cpu.index_y = 0;
+        force core_top.my_cpu.arlet_cpu.load_reg = 0;
+        force core_top.my_cpu.arlet_cpu.inc = 0;
+        force core_top.my_cpu.arlet_cpu.write_back = 0;
+        force core_top.my_cpu.arlet_cpu.load_only = 0;
+        force core_top.my_cpu.arlet_cpu.store = 0;
+        force core_top.my_cpu.arlet_cpu.adc_sbc = 0;
+        force core_top.my_cpu.arlet_cpu.compare = 0;
+        force core_top.my_cpu.arlet_cpu.shift = 0;
+        force core_top.my_cpu.arlet_cpu.rotate = 0;
+        force core_top.my_cpu.arlet_cpu.backwards = 0;
+        force core_top.my_cpu.arlet_cpu.cond_true = 0;
+        force core_top.my_cpu.arlet_cpu.cond_code = 0;
+        force core_top.my_cpu.arlet_cpu.shift_right = 0;
+        force core_top.my_cpu.arlet_cpu.alu_shift_right = 0;
+        force core_top.my_cpu.arlet_cpu.op = 0;
+        force core_top.my_cpu.arlet_cpu.alu_op = 0;
+        force core_top.my_cpu.arlet_cpu.adc_bcd = 0;
+        force core_top.my_cpu.arlet_cpu.adj_bcd = 0;
+        force core_top.my_cpu.arlet_cpu.bit_ins = 0;
+        force core_top.my_cpu.arlet_cpu.plp = 0;
+        force core_top.my_cpu.arlet_cpu.php = 0;
+        force core_top.my_cpu.arlet_cpu.clc = 0;
+        force core_top.my_cpu.arlet_cpu.sed = 0;
+        force core_top.my_cpu.arlet_cpu.cli = 0;
+        force core_top.my_cpu.arlet_cpu.sei = 0;
+        force core_top.my_cpu.arlet_cpu.clv = 0;
+        force core_top.my_cpu.arlet_cpu.brk = 0;
+        force core_top.my_cpu.arlet_cpu.res = 0;
+        force core_top.my_cpu.arlet_cpu.write_register = 0;
+        force core_top.my_cpu.arlet_cpu.ADJL = 0;
+        force core_top.my_cpu.arlet_cpu.ADJH = 0;
+        force core_top.my_cpu.arlet_cpu.NMI_1 = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.OUT = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.CO = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.N = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.HC = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.AI7 = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.BI7 = 0;
         force core_top.my_cpu.arlet_cpu.ALU.temp_logic = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.temp_BI = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.temp_l = 0;
+        force core_top.my_cpu.arlet_cpu.ALU.temp_h = 0;
 
         clk25 = 1'b0;
         uart_rx = 1'b0;
         rst_n = 1'b0;         
         #40 rst_n = 1'b1;
 
-        release core_top.my_cpu.arlet_cpu.DIHOLD;
+        release core_top.clk_div;
+        release core_top.cpu_clken;
+        release core_top.hard_reset;
+        release core_top.reset_cnt;
+        release core_top.my_cpu.arlet_cpu.AB;
         release core_top.my_cpu.arlet_cpu.PC;
+        release core_top.my_cpu.arlet_cpu.ABL;
+        release core_top.my_cpu.arlet_cpu.ABH;
+        release core_top.my_cpu.arlet_cpu.DIHOLD;
+        release core_top.my_cpu.arlet_cpu.IRHOLD;
+        release core_top.my_cpu.arlet_cpu.IRHOLD_valid;
+        release core_top.my_cpu.arlet_cpu.C;
+        release core_top.my_cpu.arlet_cpu.Z;
+        release core_top.my_cpu.arlet_cpu.I;
+        release core_top.my_cpu.arlet_cpu.D;
+        release core_top.my_cpu.arlet_cpu.V;
+        release core_top.my_cpu.arlet_cpu.N;
+        release core_top.my_cpu.arlet_cpu.AI;
+        release core_top.my_cpu.arlet_cpu.BI;
+        release core_top.my_cpu.arlet_cpu.DO;
+        release core_top.my_cpu.arlet_cpu.WE;
+        release core_top.my_cpu.arlet_cpu.CI;
+        release core_top.my_cpu.arlet_cpu.NMI_edge;
+        release core_top.my_cpu.arlet_cpu.regsel;
+        release core_top.my_cpu.arlet_cpu.PC_inc;
+        release core_top.my_cpu.arlet_cpu.PC_temp;
+        release core_top.my_cpu.arlet_cpu.src_reg;
+        release core_top.my_cpu.arlet_cpu.dst_reg;
+        release core_top.my_cpu.arlet_cpu.index_y;
+        release core_top.my_cpu.arlet_cpu.load_reg;
+        release core_top.my_cpu.arlet_cpu.inc;
+        release core_top.my_cpu.arlet_cpu.write_back;
+        release core_top.my_cpu.arlet_cpu.load_only;
+        release core_top.my_cpu.arlet_cpu.store;
+        release core_top.my_cpu.arlet_cpu.adc_sbc;
+        release core_top.my_cpu.arlet_cpu.compare;
+        release core_top.my_cpu.arlet_cpu.shift;
+        release core_top.my_cpu.arlet_cpu.rotate;
+        release core_top.my_cpu.arlet_cpu.backwards;
+        release core_top.my_cpu.arlet_cpu.cond_true;
+        release core_top.my_cpu.arlet_cpu.cond_code;
+        release core_top.my_cpu.arlet_cpu.shift_right;
+        release core_top.my_cpu.arlet_cpu.alu_shift_right;
+        release core_top.my_cpu.arlet_cpu.op;
+        release core_top.my_cpu.arlet_cpu.alu_op;
+        release core_top.my_cpu.arlet_cpu.adc_bcd;
+        release core_top.my_cpu.arlet_cpu.adj_bcd;
+        release core_top.my_cpu.arlet_cpu.bit_ins;
+        release core_top.my_cpu.arlet_cpu.plp;
+        release core_top.my_cpu.arlet_cpu.php;
+        release core_top.my_cpu.arlet_cpu.clc;
+        release core_top.my_cpu.arlet_cpu.sec;
+        release core_top.my_cpu.arlet_cpu.cld;
+        release core_top.my_cpu.arlet_cpu.sed;
+        release core_top.my_cpu.arlet_cpu.sei;
+        release core_top.my_cpu.arlet_cpu.clv;
+        release core_top.my_cpu.arlet_cpu.brk;
+        release core_top.my_cpu.arlet_cpu.res;
+        release core_top.my_cpu.arlet_cpu.write_register;
+        release core_top.my_cpu.arlet_cpu.ADJL;
+        release core_top.my_cpu.arlet_cpu.ADJH;
+        release core_top.my_cpu.arlet_cpu.NMI_1;
         release core_top.my_cpu.arlet_cpu.ALU.OUT;
+        release core_top.my_cpu.arlet_cpu.ALU.CO;
+        release core_top.my_cpu.arlet_cpu.ALU.N;
+        release core_top.my_cpu.arlet_cpu.ALU.HC;
+        release core_top.my_cpu.arlet_cpu.ALU.AI7;
+        release core_top.my_cpu.arlet_cpu.ALU.BI7;
         release core_top.my_cpu.arlet_cpu.ALU.temp_logic;
+        release core_top.my_cpu.arlet_cpu.ALU.temp_BI;
+        release core_top.my_cpu.arlet_cpu.ALU.temp_l;
+        release core_top.my_cpu.arlet_cpu.ALU.temp_h;
 
         $display("Starting...");
         $dumpfile("apple1_top_tb.vcd");

rtl/apple1.v

@@ -78,8 +78,8 @@ module apple1(
         .dbi    (dbi),
         .dbo    (dbo),
         .we     (we),
-        .irq    (1'b1),
+        .irq_n  (1'b1),
-        .nmi    (1'b1),
+        .nmi_n  (1'b1),
         .ready  (cpu_clken)
     );
 
@@ -95,6 +95,7 @@ module apple1(
     wire [7:0] ram_dout;
     ram #(RAM_FILENAME) my_ram (
         .clk(clk25),
+        .reset(reset),
         .address(ab[12:0]),
         .w_en(we & ram_cs),
         .din(dbo),
@@ -105,6 +106,7 @@ module apple1(
     wire [7:0] rom_dout;
     rom_wozmon #(WOZ_FILENAME) my_rom_wozmon (
         .clk(clk25),
+        .reset(reset),
         .address(ab[7:0]),
         .dout(rom_dout)
     );
@@ -113,6 +115,7 @@ module apple1(
     wire [7:0] uart_dout;
     uart my_uart (
         .clk(clk25),
+        .reset(reset),
 
         .uart_rx(uart_rx),
         .uart_tx(uart_tx),

rtl/cpu/arlet_6502.v

@@ -6,8 +6,8 @@ module arlet_6502(
     input [7:0] dbi,
     output reg [7:0] dbo,
     output reg we,
-    input irq,
+    input irq_n,
-    input nmi,
+    input nmi_n,
     input ready
 );
 
@@ -27,8 +27,15 @@ module arlet_6502(
         .RDY(ready) 
     );
 
-    always @(posedge clk)
+    always @(posedge clk or posedge reset)
     begin
+        if (reset)
+        begin
+            ab <= 16'd0;
+            dbo <= 8'd0;
+            we <= 1'b0;
+        end
+        else
             if (enable)
             begin
                 ab <= ab_c;

rtl/ram.v

@@ -1,5 +1,6 @@
 module ram(
     input clk,
+    input reset,
     input [12:0] address,
     input w_en,
     input [7:0] din,
@@ -15,8 +16,8 @@ module ram(
 
     always @(posedge clk)
     begin
-        dout <= ram[address];
+        dout <= reset ? 8'h0 : ram[address];
-        if (w_en) ram[address] <= din;
+        if (w_en && ~reset) ram[address] <= din;
     end
 
 endmodule

rtl/rom_wozmon.v

@@ -1,5 +1,6 @@
 module rom_wozmon(
     input clk,
+    input reset,
     input [7:0] address,
     output reg [7:0] dout
     );
@@ -13,7 +14,7 @@ module rom_wozmon(
 
     always @(posedge clk)
     begin
-        dout <= rom[address];
+        dout <= reset ? 8'h0 : rom[address];
     end
 
 endmodule

rtl/uart/async_tx_rx.v

@@ -9,6 +9,7 @@
 ////////////////////////////////////////////////////////
 module async_transmitter(
     input clk,
+    input reset,
     input TxD_start,
     input [7:0] TxD_data,
     output TxD,
@@ -31,7 +32,14 @@ module async_transmitter(
     wire TxD_ready = (TxD_state==0);
     assign TxD_busy = ~TxD_ready;
 
-    always @(posedge clk)
+    always @(posedge clk or posedge reset)
+    begin
+        if (reset)
+        begin
+            TxD_state <= 0;
+            TxD_shift <= 0;
+        end
+        else
         begin
             if(TxD_ready & TxD_start)
                 TxD_shift <= TxD_data;
@@ -55,6 +63,7 @@ module async_transmitter(
                 default: if(BitTick) TxD_state <= 4'b0000;
             endcase
         end
+    end
 
     assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);
 endmodule

rtl/uart/uart.v

@@ -6,6 +6,7 @@
 
 module uart(
     input clk,
+    input reset,
 
     input enable,
     input [1:0] address,
@@ -28,6 +29,7 @@ module uart(
 
     async_transmitter #(ClkFrequency, Baud) my_tx (
         .clk(clk),
+        .reset(reset),
         .TxD_start(uart_tx_stb),
         .TxD_data(uart_tx_byte),
         .TxD(uart_tx),
@@ -48,7 +50,14 @@ module uart(
         .RxD_endofpacket(rx_end)
         );
 
-    always @(posedge clk)
+    always @(posedge clk or posedge reset)
+    begin
+        if (reset)
+        begin
+            uart_rx_status <= 'b0;
+            uart_rx_byte <= 8'd0;
+        end
+        else
         begin
             // new byte from RX, check register is clear and CPU has seen
             // previous byte, otherwise we ignore the new data
@@ -62,6 +71,7 @@ module uart(
             if (uart_rx_ack)
                 uart_rx_status <= 'b0;
         end
+    end
 
     assign uart_cts = ~rx_idle || uart_rx_status;
 
@@ -70,7 +80,17 @@ module uart(
     localparam UART_TX   = 2'b10;
 
     // Handle Register
-    always @(posedge clk)
+    always @(posedge clk or posedge reset)
+    begin
+        if (reset)
+        begin
+            dout <= 8'd0;
+
+            uart_tx_stb <= 0;
+            uart_rx_ack <= 0;
+            uart_tx_byte <= 8'd0;
+        end
+        else
         begin
             uart_tx_stb <= 0;
             uart_rx_ack <= 0;
@@ -82,6 +102,8 @@ module uart(
                 UART_TX:
                 begin
                     // UART TX - 0xD012
+                    dout <= {uart_tx_status, 7'd0};
+
                     if (w_en)
                     begin
                         // Apple 1 terminal only uses 7 bits, MSB indicates
@@ -92,27 +114,28 @@ module uart(
                             uart_tx_stb <= 1;
                         end
                     end
-                else
-                    dout <= {uart_tx_status, 7'd0};
                 end
 
                 UART_RXCR:
                 begin
                     // UART RX CR - 0xD011
-                if (~w_en)
                     dout <= {uart_rx_status, 7'b0};
                 end
 
                 UART_RX:
                 begin
                     // UART RX - 0xD010
-                if (~w_en)
-                begin
                     dout <= {uart_rx_status, uart_rx_byte[6:0]};
+                    if (~w_en)
                         uart_rx_ack <= 1'b1;
                 end
-            end
+
+                default:
+                    dout <= 8'b0;
                 endcase
             end
+            else
+                    dout <= 8'b0;
+        end
     end
 endmodule