mirror of
https://github.com/alangarf/apple-one.git
synced 2025-02-03 17:33:51 +00:00
Yay got iverilog sim working!
This commit is contained in:
Alan Garfield
parent
c4d42fae3c
commit
bcaf9e6962
@ -32,20 +32,156 @@ module apple1_tb;
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// Setup dumping of data for inspection
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// Setup dumping of data for inspection
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initial begin
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initial begin
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force core_top.my_cpu.arlet_cpu.DIHOLD = 0;
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force core_top.clk_div = 0;
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force core_top.my_cpu.arlet_cpu.ALU.OUT = 0;
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force core_top.cpu_clken = 0;
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force core_top.hard_reset = 0;
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force core_top.reset_cnt = 0;
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force core_top.my_cpu.arlet_cpu.AB = 0;
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force core_top.my_cpu.arlet_cpu.PC = 0;
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force core_top.my_cpu.arlet_cpu.PC = 0;
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force core_top.my_cpu.arlet_cpu.ABL = 0;
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force core_top.my_cpu.arlet_cpu.ABH = 0;
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force core_top.my_cpu.arlet_cpu.DIHOLD = 0;
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force core_top.my_cpu.arlet_cpu.IRHOLD = 0;
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force core_top.my_cpu.arlet_cpu.IRHOLD_valid = 0;
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force core_top.my_cpu.arlet_cpu.C = 0;
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force core_top.my_cpu.arlet_cpu.Z = 0;
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force core_top.my_cpu.arlet_cpu.I = 0;
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force core_top.my_cpu.arlet_cpu.D = 0;
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force core_top.my_cpu.arlet_cpu.V = 0;
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force core_top.my_cpu.arlet_cpu.N = 0;
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force core_top.my_cpu.arlet_cpu.AI = 0;
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force core_top.my_cpu.arlet_cpu.BI = 0;
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force core_top.my_cpu.arlet_cpu.DO = 0;
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force core_top.my_cpu.arlet_cpu.WE = 0;
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force core_top.my_cpu.arlet_cpu.CI = 0;
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force core_top.my_cpu.arlet_cpu.NMI_edge = 0;
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force core_top.my_cpu.arlet_cpu.regsel = 0;
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force core_top.my_cpu.arlet_cpu.PC_inc = 0;
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force core_top.my_cpu.arlet_cpu.PC_temp = 0;
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force core_top.my_cpu.arlet_cpu.src_reg = 0;
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force core_top.my_cpu.arlet_cpu.dst_reg = 0;
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force core_top.my_cpu.arlet_cpu.index_y = 0;
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force core_top.my_cpu.arlet_cpu.load_reg = 0;
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force core_top.my_cpu.arlet_cpu.inc = 0;
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force core_top.my_cpu.arlet_cpu.write_back = 0;
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force core_top.my_cpu.arlet_cpu.load_only = 0;
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force core_top.my_cpu.arlet_cpu.store = 0;
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force core_top.my_cpu.arlet_cpu.adc_sbc = 0;
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force core_top.my_cpu.arlet_cpu.compare = 0;
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force core_top.my_cpu.arlet_cpu.shift = 0;
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force core_top.my_cpu.arlet_cpu.rotate = 0;
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force core_top.my_cpu.arlet_cpu.backwards = 0;
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force core_top.my_cpu.arlet_cpu.cond_true = 0;
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force core_top.my_cpu.arlet_cpu.cond_code = 0;
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force core_top.my_cpu.arlet_cpu.shift_right = 0;
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force core_top.my_cpu.arlet_cpu.alu_shift_right = 0;
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force core_top.my_cpu.arlet_cpu.op = 0;
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force core_top.my_cpu.arlet_cpu.alu_op = 0;
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force core_top.my_cpu.arlet_cpu.adc_bcd = 0;
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force core_top.my_cpu.arlet_cpu.adj_bcd = 0;
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force core_top.my_cpu.arlet_cpu.bit_ins = 0;
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force core_top.my_cpu.arlet_cpu.plp = 0;
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force core_top.my_cpu.arlet_cpu.php = 0;
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force core_top.my_cpu.arlet_cpu.clc = 0;
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force core_top.my_cpu.arlet_cpu.sed = 0;
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force core_top.my_cpu.arlet_cpu.cli = 0;
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force core_top.my_cpu.arlet_cpu.sei = 0;
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force core_top.my_cpu.arlet_cpu.clv = 0;
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force core_top.my_cpu.arlet_cpu.brk = 0;
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force core_top.my_cpu.arlet_cpu.res = 0;
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force core_top.my_cpu.arlet_cpu.write_register = 0;
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force core_top.my_cpu.arlet_cpu.ADJL = 0;
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force core_top.my_cpu.arlet_cpu.ADJH = 0;
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force core_top.my_cpu.arlet_cpu.NMI_1 = 0;
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force core_top.my_cpu.arlet_cpu.ALU.OUT = 0;
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force core_top.my_cpu.arlet_cpu.ALU.CO = 0;
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force core_top.my_cpu.arlet_cpu.ALU.N = 0;
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force core_top.my_cpu.arlet_cpu.ALU.HC = 0;
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force core_top.my_cpu.arlet_cpu.ALU.AI7 = 0;
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force core_top.my_cpu.arlet_cpu.ALU.BI7 = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_logic = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_logic = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_BI = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_l = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_h = 0;
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clk25 = 1'b0;
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clk25 = 1'b0;
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uart_rx = 1'b0;
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uart_rx = 1'b0;
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rst_n = 1'b0;
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rst_n = 1'b0;
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#40 rst_n = 1'b1;
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#40 rst_n = 1'b1;
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release core_top.my_cpu.arlet_cpu.DIHOLD;
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release core_top.clk_div;
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release core_top.cpu_clken;
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release core_top.hard_reset;
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release core_top.reset_cnt;
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release core_top.my_cpu.arlet_cpu.AB;
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release core_top.my_cpu.arlet_cpu.PC;
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release core_top.my_cpu.arlet_cpu.PC;
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release core_top.my_cpu.arlet_cpu.ABL;
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release core_top.my_cpu.arlet_cpu.ABH;
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release core_top.my_cpu.arlet_cpu.DIHOLD;
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release core_top.my_cpu.arlet_cpu.IRHOLD;
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release core_top.my_cpu.arlet_cpu.IRHOLD_valid;
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release core_top.my_cpu.arlet_cpu.C;
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release core_top.my_cpu.arlet_cpu.Z;
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release core_top.my_cpu.arlet_cpu.I;
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release core_top.my_cpu.arlet_cpu.D;
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release core_top.my_cpu.arlet_cpu.V;
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release core_top.my_cpu.arlet_cpu.N;
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release core_top.my_cpu.arlet_cpu.AI;
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release core_top.my_cpu.arlet_cpu.BI;
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release core_top.my_cpu.arlet_cpu.DO;
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release core_top.my_cpu.arlet_cpu.WE;
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release core_top.my_cpu.arlet_cpu.CI;
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release core_top.my_cpu.arlet_cpu.NMI_edge;
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release core_top.my_cpu.arlet_cpu.regsel;
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release core_top.my_cpu.arlet_cpu.PC_inc;
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release core_top.my_cpu.arlet_cpu.PC_temp;
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release core_top.my_cpu.arlet_cpu.src_reg;
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release core_top.my_cpu.arlet_cpu.dst_reg;
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release core_top.my_cpu.arlet_cpu.index_y;
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release core_top.my_cpu.arlet_cpu.load_reg;
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release core_top.my_cpu.arlet_cpu.inc;
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release core_top.my_cpu.arlet_cpu.write_back;
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release core_top.my_cpu.arlet_cpu.load_only;
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release core_top.my_cpu.arlet_cpu.store;
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release core_top.my_cpu.arlet_cpu.adc_sbc;
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release core_top.my_cpu.arlet_cpu.compare;
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release core_top.my_cpu.arlet_cpu.shift;
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release core_top.my_cpu.arlet_cpu.rotate;
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release core_top.my_cpu.arlet_cpu.backwards;
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release core_top.my_cpu.arlet_cpu.cond_true;
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release core_top.my_cpu.arlet_cpu.cond_code;
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release core_top.my_cpu.arlet_cpu.shift_right;
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release core_top.my_cpu.arlet_cpu.alu_shift_right;
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release core_top.my_cpu.arlet_cpu.op;
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release core_top.my_cpu.arlet_cpu.alu_op;
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release core_top.my_cpu.arlet_cpu.adc_bcd;
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release core_top.my_cpu.arlet_cpu.adj_bcd;
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release core_top.my_cpu.arlet_cpu.bit_ins;
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release core_top.my_cpu.arlet_cpu.plp;
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release core_top.my_cpu.arlet_cpu.php;
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release core_top.my_cpu.arlet_cpu.clc;
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release core_top.my_cpu.arlet_cpu.sec;
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release core_top.my_cpu.arlet_cpu.cld;
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release core_top.my_cpu.arlet_cpu.sed;
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release core_top.my_cpu.arlet_cpu.sei;
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release core_top.my_cpu.arlet_cpu.clv;
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release core_top.my_cpu.arlet_cpu.brk;
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release core_top.my_cpu.arlet_cpu.res;
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release core_top.my_cpu.arlet_cpu.write_register;
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release core_top.my_cpu.arlet_cpu.ADJL;
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release core_top.my_cpu.arlet_cpu.ADJH;
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release core_top.my_cpu.arlet_cpu.NMI_1;
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release core_top.my_cpu.arlet_cpu.ALU.OUT;
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release core_top.my_cpu.arlet_cpu.ALU.OUT;
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release core_top.my_cpu.arlet_cpu.ALU.CO;
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release core_top.my_cpu.arlet_cpu.ALU.N;
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release core_top.my_cpu.arlet_cpu.ALU.HC;
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release core_top.my_cpu.arlet_cpu.ALU.AI7;
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release core_top.my_cpu.arlet_cpu.ALU.BI7;
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release core_top.my_cpu.arlet_cpu.ALU.temp_logic;
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release core_top.my_cpu.arlet_cpu.ALU.temp_logic;
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release core_top.my_cpu.arlet_cpu.ALU.temp_BI;
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release core_top.my_cpu.arlet_cpu.ALU.temp_l;
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release core_top.my_cpu.arlet_cpu.ALU.temp_h;
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$display("Starting...");
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$display("Starting...");
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$dumpfile("apple1_top_tb.vcd");
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$dumpfile("apple1_top_tb.vcd");
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@ -78,8 +78,8 @@ module apple1(
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.dbi (dbi),
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.dbi (dbi),
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.dbo (dbo),
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.dbo (dbo),
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.we (we),
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.we (we),
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.irq (1'b1),
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.irq_n (1'b1),
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.nmi (1'b1),
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.nmi_n (1'b1),
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.ready (cpu_clken)
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.ready (cpu_clken)
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);
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);
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@ -95,6 +95,7 @@ module apple1(
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wire [7:0] ram_dout;
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wire [7:0] ram_dout;
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ram #(RAM_FILENAME) my_ram (
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ram #(RAM_FILENAME) my_ram (
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.clk(clk25),
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.clk(clk25),
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.reset(reset),
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.address(ab[12:0]),
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.address(ab[12:0]),
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.w_en(we & ram_cs),
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.w_en(we & ram_cs),
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.din(dbo),
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.din(dbo),
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@ -105,6 +106,7 @@ module apple1(
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wire [7:0] rom_dout;
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wire [7:0] rom_dout;
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rom_wozmon #(WOZ_FILENAME) my_rom_wozmon (
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rom_wozmon #(WOZ_FILENAME) my_rom_wozmon (
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.clk(clk25),
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.clk(clk25),
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.reset(reset),
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.address(ab[7:0]),
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.address(ab[7:0]),
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.dout(rom_dout)
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.dout(rom_dout)
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);
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);
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@ -113,6 +115,7 @@ module apple1(
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wire [7:0] uart_dout;
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wire [7:0] uart_dout;
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uart my_uart (
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uart my_uart (
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.clk(clk25),
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.clk(clk25),
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.reset(reset),
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.uart_rx(uart_rx),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_tx(uart_tx),
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@ -6,8 +6,8 @@ module arlet_6502(
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input [7:0] dbi,
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input [7:0] dbi,
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output reg [7:0] dbo,
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output reg [7:0] dbo,
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output reg we,
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output reg we,
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input irq,
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input irq_n,
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input nmi,
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input nmi_n,
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input ready
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input ready
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);
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);
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@ -27,13 +27,20 @@ module arlet_6502(
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.RDY(ready)
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.RDY(ready)
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);
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);
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always @(posedge clk)
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always @(posedge clk or posedge reset)
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begin
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begin
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if (enable)
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if (reset)
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begin
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begin
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ab <= ab_c;
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ab <= 16'd0;
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dbo <= dbo_c;
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dbo <= 8'd0;
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we <= we_c;
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we <= 1'b0;
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end
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end
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else
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if (enable)
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begin
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ab <= ab_c;
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dbo <= dbo_c;
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we <= we_c;
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end
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end
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end
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endmodule
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endmodule
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@ -1,5 +1,6 @@
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module ram(
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module ram(
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input clk,
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input clk,
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input reset,
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input [12:0] address,
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input [12:0] address,
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input w_en,
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input w_en,
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input [7:0] din,
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input [7:0] din,
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@ -15,8 +16,8 @@ module ram(
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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dout <= ram[address];
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dout <= reset ? 8'h0 : ram[address];
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if (w_en) ram[address] <= din;
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if (w_en && ~reset) ram[address] <= din;
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end
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end
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endmodule
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endmodule
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@ -1,5 +1,6 @@
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module rom_wozmon(
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module rom_wozmon(
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input clk,
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input clk,
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input reset,
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input [7:0] address,
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input [7:0] address,
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output reg [7:0] dout
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output reg [7:0] dout
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);
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);
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@ -13,7 +14,7 @@ module rom_wozmon(
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|
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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dout <= rom[address];
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dout <= reset ? 8'h0 : rom[address];
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end
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end
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endmodule
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endmodule
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@ -9,6 +9,7 @@
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////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////
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module async_transmitter(
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module async_transmitter(
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input clk,
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input clk,
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input reset,
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input TxD_start,
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input TxD_start,
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input [7:0] TxD_data,
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input [7:0] TxD_data,
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output TxD,
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output TxD,
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@ -31,29 +32,37 @@ module async_transmitter(
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wire TxD_ready = (TxD_state==0);
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wire TxD_ready = (TxD_state==0);
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assign TxD_busy = ~TxD_ready;
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assign TxD_busy = ~TxD_ready;
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|
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always @(posedge clk)
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always @(posedge clk or posedge reset)
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begin
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begin
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if(TxD_ready & TxD_start)
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if (reset)
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TxD_shift <= TxD_data;
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begin
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TxD_state <= 0;
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TxD_shift <= 0;
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end
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else
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else
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if(TxD_state[3] & BitTick)
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begin
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TxD_shift <= (TxD_shift >> 1);
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if(TxD_ready & TxD_start)
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TxD_shift <= TxD_data;
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else
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if(TxD_state[3] & BitTick)
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TxD_shift <= (TxD_shift >> 1);
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case(TxD_state)
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case(TxD_state)
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4'b0000: if(TxD_start) TxD_state <= 4'b0100;
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4'b0000: if(TxD_start) TxD_state <= 4'b0100;
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4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
|
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
|
||||||
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
|
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
|
||||||
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
|
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
|
||||||
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
|
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
|
||||||
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
|
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
|
||||||
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
|
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
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||||||
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
|
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
|
||||||
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
|
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
|
||||||
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
|
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
|
||||||
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
|
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
|
||||||
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
|
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
|
||||||
default: if(BitTick) TxD_state <= 4'b0000;
|
default: if(BitTick) TxD_state <= 4'b0000;
|
||||||
endcase
|
endcase
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);
|
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);
|
||||||
|
|||||||
105
rtl/uart/uart.v
105
rtl/uart/uart.v
@ -6,6 +6,7 @@
|
|||||||
|
|
||||||
module uart(
|
module uart(
|
||||||
input clk,
|
input clk,
|
||||||
|
input reset,
|
||||||
|
|
||||||
input enable,
|
input enable,
|
||||||
input [1:0] address,
|
input [1:0] address,
|
||||||
@ -28,6 +29,7 @@ module uart(
|
|||||||
|
|
||||||
async_transmitter #(ClkFrequency, Baud) my_tx (
|
async_transmitter #(ClkFrequency, Baud) my_tx (
|
||||||
.clk(clk),
|
.clk(clk),
|
||||||
|
.reset(reset),
|
||||||
.TxD_start(uart_tx_stb),
|
.TxD_start(uart_tx_stb),
|
||||||
.TxD_data(uart_tx_byte),
|
.TxD_data(uart_tx_byte),
|
||||||
.TxD(uart_tx),
|
.TxD(uart_tx),
|
||||||
@ -48,19 +50,27 @@ module uart(
|
|||||||
.RxD_endofpacket(rx_end)
|
.RxD_endofpacket(rx_end)
|
||||||
);
|
);
|
||||||
|
|
||||||
always @(posedge clk)
|
always @(posedge clk or posedge reset)
|
||||||
begin
|
begin
|
||||||
// new byte from RX, check register is clear and CPU has seen
|
if (reset)
|
||||||
// previous byte, otherwise we ignore the new data
|
|
||||||
if (uart_rx_stb && ~uart_rx_status)
|
|
||||||
begin
|
begin
|
||||||
uart_rx_status <= 'b1;
|
|
||||||
uart_rx_byte <= rx_data;
|
|
||||||
end
|
|
||||||
|
|
||||||
// clear the rx status flag on ack from CPU
|
|
||||||
if (uart_rx_ack)
|
|
||||||
uart_rx_status <= 'b0;
|
uart_rx_status <= 'b0;
|
||||||
|
uart_rx_byte <= 8'd0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
// new byte from RX, check register is clear and CPU has seen
|
||||||
|
// previous byte, otherwise we ignore the new data
|
||||||
|
if (uart_rx_stb && ~uart_rx_status)
|
||||||
|
begin
|
||||||
|
uart_rx_status <= 'b1;
|
||||||
|
uart_rx_byte <= rx_data;
|
||||||
|
end
|
||||||
|
|
||||||
|
// clear the rx status flag on ack from CPU
|
||||||
|
if (uart_rx_ack)
|
||||||
|
uart_rx_status <= 'b0;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
assign uart_cts = ~rx_idle || uart_rx_status;
|
assign uart_cts = ~rx_idle || uart_rx_status;
|
||||||
@ -70,49 +80,62 @@ module uart(
|
|||||||
localparam UART_TX = 2'b10;
|
localparam UART_TX = 2'b10;
|
||||||
|
|
||||||
// Handle Register
|
// Handle Register
|
||||||
always @(posedge clk)
|
always @(posedge clk or posedge reset)
|
||||||
begin
|
begin
|
||||||
uart_tx_stb <= 0;
|
if (reset)
|
||||||
uart_rx_ack <= 0;
|
|
||||||
|
|
||||||
if (enable)
|
|
||||||
begin
|
begin
|
||||||
case (address)
|
dout <= 8'd0;
|
||||||
|
|
||||||
UART_TX:
|
uart_tx_stb <= 0;
|
||||||
|
uart_rx_ack <= 0;
|
||||||
|
uart_tx_byte <= 8'd0;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
uart_tx_stb <= 0;
|
||||||
|
uart_rx_ack <= 0;
|
||||||
|
|
||||||
|
if (enable)
|
||||||
begin
|
begin
|
||||||
// UART TX - 0xD012
|
case (address)
|
||||||
if (w_en)
|
|
||||||
|
UART_TX:
|
||||||
begin
|
begin
|
||||||
// Apple 1 terminal only uses 7 bits, MSB indicates
|
// UART TX - 0xD012
|
||||||
// terminal has ack'd RX
|
dout <= {uart_tx_status, 7'd0};
|
||||||
if (~uart_tx_status)
|
|
||||||
|
if (w_en)
|
||||||
begin
|
begin
|
||||||
uart_tx_byte <= {1'b0, din[6:0]};
|
// Apple 1 terminal only uses 7 bits, MSB indicates
|
||||||
uart_tx_stb <= 1;
|
// terminal has ack'd RX
|
||||||
|
if (~uart_tx_status)
|
||||||
|
begin
|
||||||
|
uart_tx_byte <= {1'b0, din[6:0]};
|
||||||
|
uart_tx_stb <= 1;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
else
|
|
||||||
dout <= {uart_tx_status, 7'd0};
|
|
||||||
end
|
|
||||||
|
|
||||||
UART_RXCR:
|
UART_RXCR:
|
||||||
begin
|
|
||||||
// UART RX CR - 0xD011
|
|
||||||
if (~w_en)
|
|
||||||
dout <= {uart_rx_status, 7'b0};
|
|
||||||
end
|
|
||||||
|
|
||||||
UART_RX:
|
|
||||||
begin
|
|
||||||
// UART RX - 0xD010
|
|
||||||
if (~w_en)
|
|
||||||
begin
|
begin
|
||||||
dout <= {uart_rx_status, uart_rx_byte[6:0]};
|
// UART RX CR - 0xD011
|
||||||
uart_rx_ack <= 1'b1;
|
dout <= {uart_rx_status, 7'b0};
|
||||||
end
|
end
|
||||||
|
|
||||||
|
UART_RX:
|
||||||
|
begin
|
||||||
|
// UART RX - 0xD010
|
||||||
|
dout <= {uart_rx_status, uart_rx_byte[6:0]};
|
||||||
|
if (~w_en)
|
||||||
|
uart_rx_ack <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
default:
|
||||||
|
dout <= 8'b0;
|
||||||
|
endcase
|
||||||
end
|
end
|
||||||
endcase
|
else
|
||||||
|
dout <= 8'b0;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user