Apple-1-HW/verilog-apple-one
1
0
Fork 0
mirror of https://github.com/alangarf/apple-one.git synced 2024-11-07 05:05:32 +00:00
Code Issues Projects Releases Wiki Activity

Fixed bug in pc_monitor signal

Browse Source
This commit is contained in:
Niels Moseley 2018-01-27 18:15:19 +01:00
parent 1cc1920c87
commit c244a3bc5d
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rtl/cpu/arlet/cpu.v
View File

@ -32,7 +32,7 @@ output WE; // write enable
input IRQ; // interrupt request
input NMI; // non-maskable interrupt request
input RDY; // Ready signal. Pauses CPU when RDY=0
output PC_MONITOR; // signal to spy / monitor the program counter for debugging
output [15:0] PC_MONITOR; // signal to spy / monitor the program counter for debugging
/*
* internal signals