Apple-1-HW/verilog-apple-one
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Fixed reg/wire problems for Quartus.

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This commit is contained in:
Niels Moseley 2018-02-07 17:12:27 +01:00
parent 3ae84f6bc0
commit dd2c480675
3 changed files with 11 additions and 5 deletions
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8
boards/terasic_de0/apple-one.qsf
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@ -46,7 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
@ -379,4 +378,11 @@ set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart/async_tx_rx.v
set_global_assignment -name VERILOG_FILE ../../rtl/rom_wozmon.v
set_global_assignment -name VERILOG_FILE ../../rtl/ram.v
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

6
rtl/apple1.v
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@ -39,9 +39,9 @@ module apple1(
input clr_screen_btn, // active high clear screen button
output vga_h_sync, // hozizontal VGA sync pulse
output vga_v_sync, // vertical VGA sync pulse
output reg vga_red, // red VGA signal
output reg vga_grn, // green VGA signal
output reg vga_blu, // blue VGA signal
output vga_red, // red VGA signal
output vga_grn, // green VGA signal
output vga_blu, // blue VGA signal
// Debugging ports
output [15:0] pc_monitor // spy for program counter / debugging

2
rtl/vga/vga.v
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@ -42,7 +42,7 @@ module vga(
reg [4:0] vram_v_addr;
reg [4:0] vram_start_addr;
reg [4:0] vram_end_addr;
reg [4:0] vram_clr_addr;
wire [4:0] vram_clr_addr;
// vram registers
wire [10:0] vram_r_addr;