From ffad5968b6d0ddd828e4382084947dd5d567226a Mon Sep 17 00:00:00 2001
From: Alan Garfield <alan@fromorbit.com>
Date: Mon, 12 Feb 2018 08:43:29 +1100
Subject: [PATCH] moved tinyfpga rtl to rtl/boards

---
 boards/TinyFPGA_B2/{ => yosys}/Makefile                      | 0
 boards/TinyFPGA_B2/yosys/tinyfpga.pcf                        | 1 +
 rtl/boards/{ice40hx8k => ice40hx8k-b-evn}/apple1_hx8k.v      | 0
 rtl/boards/{ice40hx8k => ice40hx8k-b-evn}/clock_pll.v        | 0
 rtl/boards/{ice40hx8k => ice40hx8k-b-evn}/clock_pll_inst.v   | 0
 rtl/boards/{ice40hx8k => ice40hx8k-b-evn}/clock_pll_v.lpc    | 0
 {boards/TinyFPGA_B2 => rtl/boards/tinyfpga_b2}/apple1_hx8k.v | 0
 {boards/TinyFPGA_B2 => rtl/boards/tinyfpga_b2}/clock_pll.v   | 0
 rtl/boards/{ice40up5k => upduino}/apple1_up5k.v              | 0
 9 files changed, 1 insertion(+)
 rename boards/TinyFPGA_B2/{ => yosys}/Makefile (100%)
 create mode 120000 boards/TinyFPGA_B2/yosys/tinyfpga.pcf
 rename rtl/boards/{ice40hx8k => ice40hx8k-b-evn}/apple1_hx8k.v (100%)
 rename rtl/boards/{ice40hx8k => ice40hx8k-b-evn}/clock_pll.v (100%)
 rename rtl/boards/{ice40hx8k => ice40hx8k-b-evn}/clock_pll_inst.v (100%)
 rename rtl/boards/{ice40hx8k => ice40hx8k-b-evn}/clock_pll_v.lpc (100%)
 rename {boards/TinyFPGA_B2 => rtl/boards/tinyfpga_b2}/apple1_hx8k.v (100%)
 rename {boards/TinyFPGA_B2 => rtl/boards/tinyfpga_b2}/clock_pll.v (100%)
 rename rtl/boards/{ice40up5k => upduino}/apple1_up5k.v (100%)

diff --git a/boards/TinyFPGA_B2/Makefile b/boards/TinyFPGA_B2/yosys/Makefile
similarity index 100%
rename from boards/TinyFPGA_B2/Makefile
rename to boards/TinyFPGA_B2/yosys/Makefile
diff --git a/boards/TinyFPGA_B2/yosys/tinyfpga.pcf b/boards/TinyFPGA_B2/yosys/tinyfpga.pcf
new file mode 120000
index 0000000..332338f
--- /dev/null
+++ b/boards/TinyFPGA_B2/yosys/tinyfpga.pcf
@@ -0,0 +1 @@
+../tinyfpga.pcf
\ No newline at end of file
diff --git a/rtl/boards/ice40hx8k/apple1_hx8k.v b/rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v
similarity index 100%
rename from rtl/boards/ice40hx8k/apple1_hx8k.v
rename to rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v
diff --git a/rtl/boards/ice40hx8k/clock_pll.v b/rtl/boards/ice40hx8k-b-evn/clock_pll.v
similarity index 100%
rename from rtl/boards/ice40hx8k/clock_pll.v
rename to rtl/boards/ice40hx8k-b-evn/clock_pll.v
diff --git a/rtl/boards/ice40hx8k/clock_pll_inst.v b/rtl/boards/ice40hx8k-b-evn/clock_pll_inst.v
similarity index 100%
rename from rtl/boards/ice40hx8k/clock_pll_inst.v
rename to rtl/boards/ice40hx8k-b-evn/clock_pll_inst.v
diff --git a/rtl/boards/ice40hx8k/clock_pll_v.lpc b/rtl/boards/ice40hx8k-b-evn/clock_pll_v.lpc
similarity index 100%
rename from rtl/boards/ice40hx8k/clock_pll_v.lpc
rename to rtl/boards/ice40hx8k-b-evn/clock_pll_v.lpc
diff --git a/boards/TinyFPGA_B2/apple1_hx8k.v b/rtl/boards/tinyfpga_b2/apple1_hx8k.v
similarity index 100%
rename from boards/TinyFPGA_B2/apple1_hx8k.v
rename to rtl/boards/tinyfpga_b2/apple1_hx8k.v
diff --git a/boards/TinyFPGA_B2/clock_pll.v b/rtl/boards/tinyfpga_b2/clock_pll.v
similarity index 100%
rename from boards/TinyFPGA_B2/clock_pll.v
rename to rtl/boards/tinyfpga_b2/clock_pll.v
diff --git a/rtl/boards/ice40up5k/apple1_up5k.v b/rtl/boards/upduino/apple1_up5k.v
similarity index 100%
rename from rtl/boards/ice40up5k/apple1_up5k.v
rename to rtl/boards/upduino/apple1_up5k.v