Apple-1-HW/verilog-apple-one
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4 Commits

Author SHA1 Message Date
Alan Garfield
ea220fb9ab added uart testbench to look at cts signal 2018-02-16 13:40:46 +11:00
Olof Kindgren
3a330aeccb Remove non-existing port assignments 2018-02-12 15:19:40 +01:00
Olof Kindgren
2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
 2018-02-12 14:04:00 +01:00
Alan Garfield
120dac091b Moved test benches to tools 2018-02-12 07:02:41 +11:00