Apple-1-HW/verilog-apple-one
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84 Commits 3 Branches 0 Tags 6.9 MiB
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6 Commits

Author SHA1 Message Date
Alan Garfield
7b3c65b8d9 Fixed issue with yosys compile 2018-02-05 00:24:12 +11:00
Alan Garfield
2432225d01 Initial VGA working with the apple one output. YAY! 2018-01-31 00:48:47 +11:00
Alan Garfield
4fef9bc10b Initial VGA module, still WIP, just outputs fixed VRAM 2018-01-29 22:53:16 +11:00
Alan Garfield
b2ebc23e3a added license headers and tidied up 2018-01-29 22:15:21 +11:00
Alan Garfield
474cabbab0 Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00
Alan Garfield
2717184e71 Added yosys support again, yay for FOSS! 2018-01-29 17:45:01 +11:00