Apple-1-HW/verilog-apple-one
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151 Commits 3 Branches 0 Tags 6.9 MiB
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4 Commits

Author SHA1 Message Date
Alan Garfield
474cabbab0 Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00
Alan Garfield
0fc84e0b37 added reset logic to uart and CPU 2018-01-28 00:23:09 +11:00
Alan Garfield
bcaf9e6962 Yay got iverilog sim working! 2018-01-27 22:13:52 +11:00
Alan Garfield
7bdccf3d1a move things around. 2018-01-27 00:21:05 +11:00