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47 lines
831 B
Verilog
47 lines
831 B
Verilog
module arlet_6502(
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input clk,
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input enable,
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input reset,
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output reg [15:0] ab,
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input [7:0] dbi,
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output reg [7:0] dbo,
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output reg we,
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input irq_n,
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input nmi_n,
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input ready
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);
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wire [7:0] dbo_c;
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wire [15:0] ab_c;
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wire we_c;
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cpu arlet_cpu (
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.clk(clk),
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.reset(reset),
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.AB(ab_c),
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.DI(dbi),
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.DO(dbo_c),
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.WE(we_c),
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.IRQ(irq_n),
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.NMI(nmi_n),
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.RDY(ready)
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);
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always @(posedge clk or posedge reset)
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begin
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if (reset)
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begin
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ab <= 16'd0;
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dbo <= 8'd0;
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we <= 1'b0;
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end
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else
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if (enable)
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begin
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ab <= ab_c;
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dbo <= dbo_c;
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we <= we_c;
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end
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end
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endmodule
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