Apple-1-HW/verilog-apple-one
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verilog-apple-one/rtl/uart
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Alan Garfield 474cabbab0 Made core neater and trying to get naming better
2018-01-29 21:00:38 +11:00
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async_tx_rx.v Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00
uart.v Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00