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11 lines
177 B
Verilog
11 lines
177 B
Verilog
module MUX #(
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parameter N=1
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) (
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output wire o,
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input wire i,
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input wire [N-1:0] s,
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input wire [N-1:0] d);
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assign o = (|s) ? &(d|(~s)) : i;
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endmodule
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