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55 lines
1.7 KiB
Verilog
55 lines
1.7 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: 8KB RAM for system
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//
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// Author.....: Alan Garfield
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// Date.......: 3-2-2018
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//
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module font_rom(
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input clk, // clock signal
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input [5:0] character, // address bus
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input [3:0] pixel, // address of the pixel to output
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input [4:0] line, // address of the line to output
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output reg out // single pixel from address and pixel pos
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);
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`ifdef SIM
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parameter ROM_FILENAME = "../roms/vga_font.bin";
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`else
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parameter ROM_FILENAME = "../../roms/vga_font.bin";
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`endif
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reg [7:0] rom[0:639];
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initial
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$readmemb(ROM_FILENAME, rom, 0, 639);
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// double width of pixel by ignoring bit 0
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wire [2:0] pixel_ptr;
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assign pixel_ptr = (3'h7 - pixel[3:1]);
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// double height of pixel by ignoring bit 0
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wire [3:0] line_ptr = line[4:1];
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always @(posedge clk)
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out <= (line[0] & pixel[0]) ? rom[(character * 10) + {2'd0, line_ptr}][pixel_ptr] : 1'b0;
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endmodule
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