37 lines
764 B
Verilog
37 lines
764 B
Verilog
module apple1_top(
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input clk, // 12 MHz board clock
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input uart_rx,
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output uart_tx,
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output uart_cts,
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output [15:0] led,
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input [3:0] button
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);
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wire clk25;
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// 12MHz up to 25MHz
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clock_pll clock_pll_inst(
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.REFERENCECLK(clk),
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.PLLOUTCORE(),
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.PLLOUTGLOBAL(clk25),
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.RESET(1'b1)
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);
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wire [15:0] pc_monitor;
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assign led[7:0] = pc_monitor[7:0];
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assign led[15:8] = ~pc_monitor[15:8];
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// apple one main system
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apple1 my_apple1(
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.clk25(clk25),
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.rst_n(1'b1),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts),
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.pc_monitor(pc_monitor),
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.reset_button(button[0])
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);
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endmodule
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