28 lines
500 B
Verilog
28 lines
500 B
Verilog
module ram(
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input clk,
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input [12:0] address,
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input w_en,
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input [7:0] din,
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output reg [7:0] dout
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);
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`ifdef YOSYS
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parameter RAM_FILENAME = "../../roms/ram.hex";
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`else
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parameter RAM_FILENAME = "../roms/ram.hex";
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`endif
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reg [7:0] ram_data[0:8191];
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initial
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$readmemh(RAM_FILENAME, ram_data, 0, 8191);
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always @(posedge clk)
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begin
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dout <= ram_data[address];
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if (w_en) ram_data[address] <= din;
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end
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endmodule
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