22 lines
411 B
Verilog
22 lines
411 B
Verilog
module rom_basic(
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input clk,
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input [11:0] address,
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output reg [7:0] dout
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);
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`ifdef YOSYS
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parameter BASIC_FILENAME = "../../roms/basic.hex";
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`else
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parameter BASIC_FILENAME = "../roms/basic.hex";
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`endif
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reg [7:0] rom_data[0:4095];
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initial
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$readmemh(BASIC_FILENAME, rom_data, 0, 4095);
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always @(posedge clk)
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dout <= rom_data[address];
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endmodule
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