116 lines
3.4 KiB
Verilog
116 lines
3.4 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple 1 implementation for the iCE40HX8K dev
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// board.
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//
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// Author.....: Alan Garfield
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// Date.......: 21-10-2018
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//
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module apple1_top #(
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parameter BASIC_FILENAME = "../../../roms/basic.hex",
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
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parameter RAM_FILENAME = "../../../roms/ram.hex",
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
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) (
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input clk, // 16 MHz board clock
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// I/O interface to computer
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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output vga_red, // red VGA signal
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output vga_grn, // green VGA signal
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output vga_blu, // blue VGA signal
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inout lt_dat,
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inout lt_env
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);
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wire clk25;
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// 16MHz up to 25MHz
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clock_pll clock_pll_inst(
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.REFERENCECLK(clk),
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.PLLOUTGLOBAL(clk25),
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.RESET(1'b1)
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);
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// lighthouse sensor
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wire lt_data_rw;
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wire lt_data_in, lt_data_out;
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SB_IO #(
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.PIN_TYPE(6'b101001),
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.PULLUP(1'b1)
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) lt_dat_io (
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.PACKAGE_PIN(lt_dat),
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.OUTPUT_ENABLE(lt_data_rw),
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.D_IN_0(lt_data_in),
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.D_OUT_0(lt_data_out)
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);
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wire lt_env_rw;
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wire lt_env_in, lt_env_out;
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SB_IO #(
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.PIN_TYPE(6'b101001),
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.PULLUP(1'b1)
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) lt_env_io (
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.PACKAGE_PIN(lt_env),
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.OUTPUT_ENABLE(lt_env_rw),
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.D_IN_0(lt_env_in),
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.D_OUT_0(lt_env_out)
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);
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assign lt_data_rw = 1'b0;
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assign lt_data_out = 1'b0;
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assign lt_env_rw = 1'b0;
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assign lt_env_out = 1'b0;
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// program counter
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wire pc_monitor;
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// apple one main system
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apple1 #(
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.BASIC_FILENAME (BASIC_FILENAME),
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.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
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.RAM_FILENAME (RAM_FILENAME),
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.VRAM_FILENAME (VRAM_FILENAME),
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.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
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) my_apple1(
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.clk25(clk25),
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.rst_n(1'b1),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.ps2_clk(1'b0),
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.ps2_din(1'b0),
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.ps2_select(1'b1),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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.vga_grn(vga_grn),
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.vga_blu(vga_blu),
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.vga_cls(1'b0),
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.pc_monitor(pc_monitor)
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);
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endmodule
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